Gossip NoC -- Avoiding Timing Side-Channel Attacks through Traffic Management

Abstract

Abstract-The wide use of Multi-processing systems-on-chip (MPSoCs) in embedded systems and the trend to increase the integration between devices have turned these systems vulnerable to attacks. Malicious software executed on compromised IP may become a serious security problem. By snooping the traffic exchanged through the Network-on-chip (NoC), it is possible to infer sensitive information such as secrets keys. NoCs are vulnerable to side channel attacks that exploit traffic interference as timing channels. When multiple IP cores are infected, they can work coordinately to implement a distributed timing attack (DTA). In this work we present for the first time the execution of a DTA and a secure enhanced NoC architecture able to avoid the timing attacks. Results show that our NoC proposal can avoid the DTA with an increase of only 1% in area and 0.8% in power regarding the whole chip design.

Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack

“…By monitoring the NoC traffic throughput the sensitive information is leaked. In addition, in this work we verify the timing security of a low area overhead timing protected NoC Gossip NoC [17]. The main contributions of our work are:…”

Side-channel protected MPSoC through secure real-time networks-on-chip

“…As a consequence of the malicious traffic, delays in the communication are caused and thus the malicious packets transmission is also delayed. At an endpoint at the other non-secured core, the adversary is able to measure the latency of their malicious traffic and infer how many collisions This threat model is not new, and its variations have also been used in best-effort NoC-based systems by [15], [16], [7]. The timing nature of the threat is also the same used in hard real-time uniprocessor systems by [17].…”

“…This triggers a cache attack, where the attacker perform a read request to the shared memory in IP 0 in step (6). As is [7] and [6], by reading the shared cache in step (7), the attacker can identify the memory sets accessed due the AES encryption. As a result a key candidate is obtained.…”

“…Cache hierarchies and NoC are a common target in timing side-channel attacks. In general, NoC communication can be exploited to optimize cache attacks, as demonstrated in [7] and [8]. In this paper, security is used as a driver to optimise hard real-time NoC design.…”

A JSON Token-Based Authentication and Access Management Schema for Cloud SaaS Applications

“…Timing Attacks: An analytical side-channel attack that exploits computational and communication data interactions on crypto-processing systems [25]. Ensuring all received JWTs are duly verified in a lucid and succinct verification contract of allowed crypto "alg", and other payload/header data cum the use of the "kid" makes the verification cut in stone without undergoing unauthorized mutation.…”