GP-SIMD Processing-in-Memory

Morad, Amir; Yavits, Leonid; Ginosar, Ran

doi:10.1145/2686875

Cited by 37 publications

(17 citation statements)

References 56 publications

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“…NMC is enabled by new memory technologies, such as 3D-stacked memories [5,62,65,66,81], and also by cache-coherent interconnects [24,88,93], which allow close integration of processing units and memory units. Depending on the applications and systems of interest (e.g., [13,14,15,22,23,27,29,31,40,42,49,50,53,58,61,68,69,71,74,77,87]), prior works propose di erent types of near-memory processing units, such as general-purpose CPU cores [13,16,27,28,29,39,64,69,78,83,86], GPU cores [44,52,80,106], recon gurable units [41,55,57,90], or xed-function units…”

Section: Related Workmentioning

confidence: 99%

NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling

Singh¹,

Diamantopoulos²,

Hagleitner³

et al. 2020

Preprint

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Ongoing climate change calls for fast and accurate weather and climate modeling. However, when solving large-scale weather prediction simulations, state-of-the-art CPU and GPU implementations su er from limited performance and high energy consumption. These implementations are dominated by complex irregular memory access patterns and low arithmetic intensity that pose fundamental challenges to acceleration. To overcome these challenges, we propose and evaluate the use of near-memory acceleration using a recon gurable fabric with high-bandwidth memory (HBM). We focus on compound stencils that are fundamental kernels in weather prediction models. By using high-level synthesis techniques, we develop NERO, an FPGA+HBM-based accelerator connected through IBM CAPI2 (Coherent Accelerator Processor Interface) to an IBM POWER9 host system. Our experimental results show that NERO outperforms a 16-core POWER9 system by 4.2× and 8.3× when running two di erent compound stencil kernels. NERO reduces the energy consumption by 22× and 29× for the same two kernels over the POWER9 system with an energy e ciency of 1.5 GFLOPS/Watt and 17.3 GFLOPS/Watt. We conclude that employing near-memory acceleration solutions for weather prediction modeling is promising as a means to achieve both high performance and high energy e ciency.

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Section: Related Workmentioning

confidence: 99%

NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling

Singh¹,

Diamantopoulos²,

Hagleitner³

et al. 2020

Preprint

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“…The PIM core could be an SIMD machine, a GPU-like multithreading machine [4], a reconfigurable array, many core systems, etc. References [26,27] also states that an SIMD/VLIW/vector processor is fit for the data-processing unit in a PIM system. The host CPU and PIM cores share the same physical memory.…”

Section: Target Architecturementioning

confidence: 99%

A Processing-in-Memory Architecture Programming Paradigm for Wireless Internet-of-Things Applications

Yang

Hou

2019

Sensors

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The widespread applications of the wireless Internet of Things (IoT) is one of the leading factors in the emerging of Big Data. Huge amounts of data need to be transferred and processed. The bandwidth and latency of data transfers have posed a new challenge for traditional computing systems. Under Big Data application scenarios, the movement of large scales of data would influence performance, power efficiency, and reliability, which are the three fundamental attributes of a computing system. Thus, changes in the computing paradigm are demanding. Processing-in- Memory (PIM), aiming at placing computation as close as possible to memory, has become of great interest to academia as well as industries. In this work, we propose a programming paradigm for PIM architecture that is suitable for wireless IoT applications. A data-transferring mechanism and middleware architecture are presented. We present our methods and experiences on simulation-platform design, as well as FPGA demo design, for PIM architecture. Typical applications in IoT, such as multimedia and MapReduce programs, are used as demonstration of our method’s validity and efficiency. The programs could successfully run on the simulation platform built based on Gem5 and on the FPGA demo. Results show that our method could largely reduce power consumption and execution time for those programs, which is very beneficial in IoT applications.

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“…To work around the limitations presented by cache coherence, most prior works assume a limited amount of sharing between the PIM kernels and the processor threads of an application. Thus, they sidestep coherence by employing solutions that restrict PIM to execute on non-cacheable data (e.g., [2,47,52,149,243]) or force processor cores to flush or not access any data that could potentially be used by PIM (e.g., [3,4,28,47,51,59,67,68,163,172,195,196,199,200]). In fact, the IMPICA accelerator design, described in Section 3, falls into the latter category.…”

Section: Lazypim: An Efficient Cache Coherence Mechanism For Processi...mentioning

confidence: 99%

Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions

Ghose¹,

Hsieh²,

Boroumand³

et al. 2018

Preprint

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Performance improvements from DRAM technology scaling have been lagging behind the improvements from logic technology scaling for many years. As application demand for main memory continues to grow, DRAM-based main memory is increasingly becoming a larger system bottleneck in terms of both performance and energy consumption. A major reason for poor memory performance and energy efficiency is memory's inability to perform computation. Instead, data stored within DRAM memory must be moved into the CPU before any computation can take place. This data movement is costly, as it requires a high latency and consumes significant energy to transfer the data across the pin-limited memory channel. Moreover, the data moved to the CPU is often not reused, and thus does not benefit from being cached within the CPU, which makes it difficult to amortize the overhead of data movement.Modern 3D-stacked DRAM architectures provide an opportunity to avoid unnecessary data movement between memory and the CPU. These multi-layer architectures include a logic layer, where compute logic can be integrated underneath multiple layers of DRAM cell arrays (i.e., the memory layers) within the same chip. Architects can take advantage of the logic layer to perform processing-in-memory (PIM), or near-data processing, where some of the computation is moved from the CPU to the logic layer underneath the memory layer. In a PIM architecture, the logic layer within DRAM has access to the high internal bandwidth available within 3D-stacked DRAM (which is much greater than the bandwidth available in the narrow memory channel between DRAM and the CPU). Thus, PIM architectures can effectively free up valuable bandwidth on the bandwidth-limited memory channel while at the same time reducing system energy consumption.A number of important issues arise when we add compute logic to DRAM. In particular, logic within DRAM does not have low-latency access to common CPU structures that are essential for modern application execution, such as the virtual memory mechanisms, e.g., the translation lookaside buffer (TLB) or the page table walker, and the cache coherence mechanisms, e.g., the coherence directory. To ease the widespread adoption of PIM, we ideally would like to maintain traditional virtual memory abstractions and the shared memory programming model. This requires efficient mechanisms that can provide logic in DRAM with access to virtual memory and cache coherence without having to communicate frequently with the CPU, as off-chip communication between the CPU and DRAM consumes much of the limited bandwidth that PIM aims to avoid using. To this end, we propose and evaluate two general-purpose solutions that can be used by PIM architectures to minimize unnecessary off-chip communication. The first, IMPICA, is an efficient in-memory accelerator for pointer chasing, which can handle address translation entirely within DRAM. The second, LazyPIM, provides coherence support without the need to continually communicate with the CPU. We show that both of these mecha...

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GP-SIMD Processing-in-Memory

Cited by 37 publications

References 56 publications

NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling

NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling

A Processing-in-Memory Architecture Programming Paradigm for Wireless Internet-of-Things Applications

Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions

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