GPUWattch

Leng, Jingwen; Hetherington, Tayler; ElTantawy, Ahmed; Gilani, Syed Zohaib; Kim, Nam Sung; Aamodt, Tor M.; Reddi, Vijay Janapa

doi:10.1145/2485922.2485964

Cited by 375 publications

(20 citation statements)

References 28 publications

(38 reference statements)

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“…We use the default GTX 480 configuration provided by the simulator. Power Simulation We use GPUWattch [16,17] for the power simulation. GPUWattch is integrated with GPGPU-Sim for cycle-level power calculation.…”

Section: Experimental Methodologymentioning

confidence: 99%

GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures

Leng

Reddi

2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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Energy efficiency is undoubtedly important for GPU architectures. Besides the traditionally explored energy-efficiency optimization techniques, exploiting the supply voltage guardband remains a promising yet unexplored opportunity. Our hardware measurements show that up to 23% of the nominal supply voltage can be eliminated to improve GPU energy efficiency by as much as 25%. The key obstacle for exploiting this opportunity lies in understanding the characteristics and root causes of large voltage droops in GPU architectures and subsequently smoothing them away without severe performance penalties. The GPU's manycore nature complicates the voltage noise phenomenon, and its distinctive architecture features from the CPU necessitate a GPU-specific voltage noise analysis. In this paper, we make the following contributions. First, we provide a voltage noise categorization framework to identify, characterize, and understand voltage noise in the manycore GPU architecture. Second, we perform a microarchitecture-level voltage-droop root-cause analysis for the two major droop types we identify, namely the local first-order droop and the global second-order droop. Third, on the basis of our categorization and characterization, we propose a hierarchical voltage smoothing mechanism that mitigates each type of voltage droop. Our evaluation shows it can reduce up to 31% worst-case droop, which translates to 11.8% core-level and 7.8% processor-level energy reduction. 161978-1-4799-8930-0/15/$31.00 ©2015 IEEE

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Section: Experimental Methodologymentioning

confidence: 99%

GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures

Leng

Reddi

2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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“…As followed in previous works Jaleel et al 2010;Lee and Kim 2012], early finishing benchmarks continue to execute until all benchmarks execute the specified number of instructions. We utilize McPAT [Li et al 2009] and GPUWattch [Leng et al 2013] for studying on-chip energy consumption, and DRAMSim2 [Rosenfeld et al 2011] to calculate off-chip DRAM energy consumption.…”

Section: Experimental Methodologymentioning

confidence: 99%

Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor

Holey

Mekkat

Yew

et al. 2015

ACM Trans. Archit. Code Optim.

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Heterogeneous multicore processors that integrate CPU cores and data-parallel accelerators such as graphic processing unit (GPU) cores onto the same die raise several new issues for sharing various on-chip resources. The shared last-level cache (LLC) is one of the most important shared resources due to its impact on performance. Accesses to the shared LLC in heterogeneous multicore processors can be dominated by the GPU due to the significantly higher number of concurrent threads supported by the architecture. Under current cache management policies, the CPU applications' share of the LLC can be significantly reduced in the presence of competing GPU applications. For many CPU applications, a reduced share of the LLC could lead to significant performance degradation. On the contrary, GPU applications can tolerate increase in memory access latency when there is sufficient thread-level parallelism (TLP). In addition to the performance challenge, introduction of diverse cores onto the same die changes the energy consumption profile and, in turn, affects the energy efficiency of the processor.In this work, we propose heterogeneous LLC management (HeLM), a novel shared LLC management policy that takes advantage of the GPU's tolerance for memory access latency. HeLM is able to throttle GPU LLC accesses and yield LLC space to cache-sensitive CPU applications. This throttling is achieved by allowing GPU accesses to bypass the LLC when an increase in memory access latency can be tolerated. The latency tolerance of a GPU application is determined by the availability of TLP, which is measured at runtime as the average number of threads that are available for issuing. For a baseline configuration with two CPU cores and four GPU cores, modeled after existing heterogeneous processor designs, HeLM outperforms least recently used (LRU) policy by 10.4%. Additionally, HeLM also outperforms competing policies. Our evaluations show that HeLM is able to sustain performance with varying core mix.In addition to the performance benefit, bypassing also reduces total accesses to the LLC, leading to a reduction in the energy consumption of the LLC module. However, LLC bypassing has the potential to increase off-chip bandwidth utilization and DRAM energy consumption. Our experiments show that HeLM exhibits better energy efficiency by reducing the ED 2 by 18% over LRU while impacting only a 7% increase in off-chip bandwidth utilization.

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“…To analyze power/energy consumption, we instrumented the GPGPUsim to collect the statistics including vector register file accesses, ALU operations, different types of memory accesses, the number of IRB accesses and the number of SRF accesses. We then modified McPAT [14] using the similar approach to GPUWattch [13] to compute the area overhead and energy/power consumption. The resulting area and the energy per access of the VRF and the SRF using the 40nm technology are shown in Table 2.…”

Section: Experimental Methodologymentioning

confidence: 99%

Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement

Xiang

Yang

Mantor

et al. 2013

Proceedings of the 27th International ACM Conference on International Conference on Supercomputing

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State-of-art graphics processing units (GPUs) employ the singleinstruction multiple-data (SIMD) style execution to achieve both high computational throughput and energy efficiency. As previous works have shown, there exists significant computational redundancy in SIMD execution, where different execution lanes operate on the same operand values. Such value locality is referred to as uniform vectors. In this paper, we first show that besides redundancy within a uniform vector, different vectors can also have the identical values. Then, we propose detailed architecture designs to exploit both types of redundancy. For redundancy within a uniform vector, we propose to either extend the vector register file with token bits or add a separate small scalar register file to eliminate redundant computations as well as redundant data storage. For redundancy across different uniform vectors, we adopt instruction reuse, proposed originally for CPU architectures, to detect and eliminate redundancy. The elimination of redundant computations and data storage leads to both significant energy savings and performance improvement. Furthermore, we propose to leverage such redundancy to protect arithmetic-logic units (ALUs) and register files against hardware errors. Our detailed evaluation shows that our proposed design has low hardware overhead and achieves performance gains, up to 23.9% and 12.0% on average, along with energy savings, up to 24.8% and 12.6% on average, as well as a 21.1% and 14.1% protection coverage for ALUs and register files, respectively.

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GPUWattch

Cited by 375 publications

References 28 publications

GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures

GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures

Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor

Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement

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