GraFBoost: Using Accelerated Flash Storage for External Graph Analytics

Jun, Sang-Woo; Wright, Andrew K.; Zhang, Sizhuo; Xu, Shuotao; Arvind, .

doi:10.1109/isca.2018.00042

Cited by 73 publications

(27 citation statements)

References 58 publications

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“…Authors propose sort-reduce algorithm to solve the random read-modify update into vertex data in the vertex-centric programming model. The algorithm is then accelerated on FPGA that uses flash memory for edges, vertices and partially sort-reduced files [66]. However, the platform does not support dynamic task loading, similar to [36], and has limited OS-level flexibility.…”

Section: Re-configurable Unitmentioning

confidence: 99%

Near-memory computing: Past, present, and future

Singh

Chelini

Corda

et al. 2019

Microprocessors and Microsystems

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The conventional approach of moving data to the CPU for computation has become a significant performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in 3D integration technologies has made the decade-old concept of coupling compute units close to the memory -called nearmemory computing (NMC) -more viable. Processing right at the "home" of data can significantly diminish the data movement problem of data-intensive applications.In this paper, we survey the prior art on NMC across various dimensions (architecture, applications, tools, etc.) and identify the key challenges and open issues with future research directions. We also provide a glimpse of our approach to near-memory computing that includes i) NMC specific microarchitecture independent application characterization ii) a compiler framework to offload the NMC kernels on our target NMC platform and iii) an analytical model to evaluate the potential of NMC.

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Section: Re-configurable Unitmentioning

confidence: 99%

Near-memory computing: Past, present, and future

Singh

Chelini

Corda

et al. 2019

Microprocessors and Microsystems

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“…There is an amount of work that has taken this issue into account, and a series of solutions are further proposed [25,26,28,32,80,94] . These solutions can be typically divided into three categories: the out-of-core solution, the multi-accelerators solution, and the heterogeneous solution.…”

Section: Large-scale Graph Processing Accelerationmentioning

confidence: 99%

“…Therefore, toward graph accelerators, using any external storages or memories that can store large realworld graphs can be considered potentially-useful as their out-of-core solutions. Graph accelerators can use disks, flashes or other external storage devices to store extremely large scale graphs [4,5,26,55,94] . However, one of the most important issues for utilizing these devices is to reduce the transmission cost of I/Os between the disk and the DRAM since the bandwidths of these devices is often significantly lower than DRAM.…”

Section: Large-scale Graph Processing Accelerationmentioning

confidence: 99%

“…Then the large graph is specially partitioned in order to fit for the processing scheme. GraFBoost [94] adopts the flash to scale to much larger graphs and mainly focuses on optimizing the random accesses. The key component is a sortreduce module that converts small random accesses into large block sequential accesses to the flash storage.…”

Section: Large-scale Graph Processing Accelerationmentioning

confidence: 99%

“…The key component is a sortreduce module that converts small random accesses into large block sequential accesses to the flash storage. It is mentioned that GraFBoost [94] embeds the accelerator into the flash for better scalability. Similar methods have been explored to accelerate the processing in database [105,106] .…”

Section: Large-scale Graph Processing Accelerationmentioning

confidence: 99%

See 2 more Smart Citations

A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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Graph is a well known data structure to represent the associated relationships in a variety of applications, e.g., data science and machine learning. Despite a wealth of existing efforts on developing graph processing systems for improving the performance and/or energy efficiency on traditional architectures, dedicated hardware solutions, also referred to as graph processing accelerators, are essential and emerging to provide the benefits significantly beyond those pure software solutions can offer. In this paper, we conduct a systematical survey regarding the design and implementation of graph processing accelerator. Specifically, we review the relevant techniques in three core components toward a graph processing accelerator: preprocessing, parallel graph computation and runtime scheduling. We also examine the benchmarks and results in existing studies for evaluating a graph processing accelerator. Interestingly, we find that there is not an absolute winner for all three aspects in graph acceleration due to the diverse characteristics of graph processing and complexity of hardware configurations. We finially present to discuss several challenges in details, and to further explore the opportunities for the future research.

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