Graph Minor Approach for Application Mapping on CGRAs

Abstract

Coarse-Grained Reconfigurable Arrays (CGRAs) exhibit high performance, improved flexibility, low cost, and power efficiency for various application domains. Compute-intensive loop kernels, which are perfect candidates to be executed on CGRAs, are usually mapped through modified modulo scheduling algorithms. These algorithms should be capable of performing both placement and routing. We formalize the CGRA mapping problem as a graph minor containment problem. We essentially test whether the dataflow graph representing the loop kernel is a minor of the modulo routing resource graph representing the CGRA resources and their interconnects. We design an exact graph minor testing approach that exploits the unique properties of both the dataflow graph and the routing resource graph to significantly prune the search space. We introduce additional heuristic strategies that drastically improve the compilation time while still generating optimal or near-optimal mapping solutions. Experimental evaluation confirms the efficiency of our approach.

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

“…Additionally, for a 5 Mega-pixel image, which is a common size nowadays, the binary translation overhead is insignificant (0.06%). Table 2 presents average number of clock cycles required to process one DFG node, in orders of magnitude, for nine modulo scheduling approaches found in literature: DRESC [27]; EMS [32]; RF [9]; RAM [29]; MSPR [11]; G -Minor [8]; EPImap [14]; REGIMap [16]; MS JIT [10]. Moreover, Table 2 presents our BT MS approach and a trace-based binary translation (TBT) proposed in [4].…”

“…Moreover, Table 2 presents our BT MS approach and a trace-based binary translation (TBT) proposed in [4]. The number of cycles were obtained from the respective references, with exception of DRESC, which time results were based on information reported in [8,29]. The results show that with MS JIT [10] and our BT MS, a reduction ranging from two to six orders of magnitude was achieved.…”

“…Using local register files connected to processing elements: Reduces the overhead of accessing centralized general-purpose register files. This solution is also used in other approaches [8,9,16,20,31,32]. 5.…”

“…During the last decade, several MS algorithms have been proposed, and most of them use mesh or mesh-plus topologies. The processing elements can be homogeneous [9,12,14,18,23,27,29,31] or heterogeneous [1,8,21,32,36]. However, the MS algorithms proposed in those previous works are highly time consuming, due to the selected scheduling approach, as well as due to their slow placement and routing steps (P&R).…”

“…To the best of our knowledge, this is the first work to propose a BT run-time modulo scheduling algorithm for CGRAs. The proposed BT MS algorithm reduces mapping time by proposing alternatives to many of the complex solutions presented in previous modulo scheduling algorithms [8,9,11,14,27,29,32]:…”