Green Secure Processors: Towards Power-Efficient Secure Processor Design

Chhabra, Siddhartha; Solihin, Yan

doi:10.1007/978-3-642-17499-5_13

Cited by 5 publications

(6 citation statements)

References 19 publications

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“…Indeed, thanks to novel effective methods and techniques for energy efficiency, the most recent computerized systems can maintain high performances for the same Watt unit [7]. It could seem that if the factor of performance per Watt does not improve over time, the electrical costs for keeping the systems in an active state would end-up much higher than the price of the hardware [8,9].…”

Section: Introductionmentioning

confidence: 99%

Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

et al. 2018

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Both computational performances and energy efficiency are required for the development of any mobile or embedded information processing system. The Internet of Things (IoT) is the latest evolution of these systems, paving the way for advancements in ubiquitous computing. In a context in which a large amount of data is often analyzed and processed, it is mandatory to adapt node logic and processing capabilities with respect to the available energy resources. This paper investigates under which conditions a partially reconfigurable hardware accelerator can provide energy saving in complex processing tasks. The paper also presents a useful analysis of how the dynamic partial reconfiguration technique can be used to enable energy efficiency in a generic IoT node that exploits a Field Programmable Gate Array (FPGA) device. Furthermore, this work introduces a hardware infrastructure and new energy metrics tailored for the energy efficiency evaluation of the dynamic partial reconfiguration process in embedded FPGA based devices. Exploiting the ability of reconfiguring circuit portions at runtime, the latest generation of FPGAs can be used to foster a better balance between energy consumption and performance. More specifically, the design methodology for the implemented digital signal processing application was adapted for the ZedBoard. To this aim, a case study of a video filtering system is proposed and analyzed by dynamically loading three different hardware filters from the management software running on a Linux-based device. With more details, the presented analytical framework allows for a direct comparison between the energy efficiency of a dynamic partially reconfigurable device and a static non-reconfigurable one. The estimated timing conditions that allow the dynamic partially reconfigurable process to achieve relevant energy efficiency with respect to the corresponding static architecture are also outlined.

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Section: Introductionmentioning

confidence: 99%

Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

et al. 2018

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“…to external memory) are encrypted [33]. Although a number of memory encryption schemes have been proposed [34][35][36], they entail significant performance overhead (up to 25% performance overhead) [37]. Protection from replay, spoofing and splicing attacks can be achieved through memory authentication schemes that perform runtime integrity verification [7].…”

Section: Technical Challengesmentioning

confidence: 99%

“…The integrity of the code and data in memory is protected by maintaining memory integrity trees in order to preserve the state of the application. However, these security mechanisms are often computationally intensive and account for excessive memory access [37]. As memory accesses of code/data contribute to the largest fraction of energy consumed in embedded processors [38], such methods are often infeasible for embedded systems with tight functional constraints.…”

Section: Technical Challengesmentioning

confidence: 99%

“…Typical memory authentication schemes employ an integrity tree to perform runtime integrity verification [37]. Authentication methods like hash function, Message authentication code (MAC), Block-level AREA are used to realize the integrity trees [34,72].…”

Section: Memory Authentication Schemesmentioning

confidence: 99%

“…Existing tree techniques include HASH trees, Parallelizable authentication (PAT) trees, and Temper evident counter (TEC)-tree [7]. However, implementing such integrity trees significantly increases runtime and memory overhead [37,73], making them infeasible for embedded systems with tight energy constraints. Therefore, runtime integrity checking has been identified as one of the leading open issues for trusted computing in mobile devices [39].…”

Section: Memory Authentication Schemesmentioning

confidence: 99%

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Securing untrusted memories in embedded systems

Vig¹

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Firstly, I would like to express my deepest gratitude to my advisor Dr. Lam Siew-Kei for his patience and continuous support during my doctoral thesis. All through my PhD, he has guided me at each step from delving deeper into technical issues, providing a high-level view of my research, to editing my manuscripts. My thesis would not have been the same without his supervision.Besides my advisor, I would like to sincerely thank Rohan Juneja, who has helped me to construct the way of my work and research efficiently. I would also like to express gratitude to Dr. Guiyuan Jiang for his continuous advice.Next, I would like to thank my friends at NTU -Nimisha, Kratika, and Tushar, who have always provided me guidance and helped me through all hurdles.Finally, I would like to thank my family: my grandparents, parents, and sister. They have always encouraged me and stood by me in whatever I pursue. Their affection and support for me, during my PhD and even otherwise in my life, is immeasurable. Special thanks to Vardhman, and Prerna, who have been like family to me these past four years in Singapore and have made this journey immensely memorable.

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Energy Efficient Memory Authentication Mechanism in Embedded Systems

Nimgaonkar

Gomathisankaran

2011

2011 International Symposium on Electronic System Design

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The pervasiveness of modern day embedded systems has led to the storing of huge amount of sensitive information in them. These embedded devices have to often operate under insecure environments and hence are susceptible to software and physical attacks. Hence security becomes a prime concern in embedded systems. Although a lot of hardware cryptographic techniques have been proposed to provide high levels of security, they are hampered by the trade-offs created by the energy constraints in embedded systems. In this paper, we propose an Energy Efficient Memory Integrity Verification Mechanism that can adaptively tune a Memory Integrity Verification Module(MIV) to a Sensor Module(SM). This drastically reduces the energy overheads imposed on an embedded system as compared to the conventional security mechanisms. The simulation results help us conclude that the average energy saved in our mechanism ranges from 88% to 99%. This is much higher as compared to the results achieved in baseline simulations with traditional memory integrity verification techniques.

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Green Secure Processors: Towards Power-Efficient Secure Processor Design

Cited by 5 publications

References 19 publications

Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

Securing untrusted memories in embedded systems

Energy Efficient Memory Authentication Mechanism in Embedded Systems

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