Ground bounce study of 304 lead interposer MQFP with on-chip decoupling capacitor test die

Abstract

Bias 0.0v 0.3v San Jose, CA 95 13 1 (Tel) 408-434-32 8 5 1.ov 3.0v 5.ov ' 8.5 6.8 6.1 AbstractAs clock frequency and the number of YO'S increase in ASIC devices, the ground bounce problems of packages begin to seriously impact system performance. To resolve these problems, high performance packages must be used in system design. This, however, can add significantly to the cost of the system. One of the methods to optimize the cost, manufacturability and the performance of packages is to add decoupling capacitors to the power and the ground of the die or packages. However, adding decoupling capacitors always increases the inductance effects. A systematic approach is needed to determine the correct method of using the decoupling capacitor technique with minimal inductive effects. 0.0V 0.3V 1.0V 3.OV 5.OV