Group delay as an estimate of delay in logic

Vlach, J.; Barby, J.A.; Vannelli, A.; Talkhan, T.; Shi, C.-J.R.

doi:10.1109/43.87605

Cited by 18 publications

(8 citation statements)

References 6 publications

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“…In some special cases there is still a simple relationship between Elmore delay and t 50 , as in the case of the RC-line interconnect model [5]. Certainly t 50 can be determined from the frequency domain data by inverse Fourier-or Laplacetransform or by transient simulation, if the model also works in the time domain.…”

Section: Theorymentioning

confidence: 98%

Estimation of the Interconnect Jitter Performance by Frequency Domain Behaviour

Tanskanen¹

2002

Proceedings: 6th IEEE Workshop on Signal Propagation on Interconnects

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This paper describes a simple frequency-domain method for estimating the jitter performance of high-speed digital interconnects. For determination of the jitter at zero crossing of differential signals, 50% unit step response delay and group delays on at least two discrete frequencies, as well as the magnitude of the interconnect transfer function on those frequencies, are required The method is verified by comparing the frequency domain results with those given by transient simulation. IntroductionA common problem in the design of the high-speed digital interconnects is how far the data can be transmitted at a certain bit rate via an interconnect. Various rule-of-thumb -style design rules are given in the literature. In [1] minimum rise time t r. is calculated from the -3dB point of the interconnect frequency response and the data pulse length is set to 3t r . to accommodate suitable margins for the jitter and dispersion. In [2] bandwidth requirements for a certain pulse rise time and rise times for one-pole and two-pole critically damped responses are considered Evaluation of the jitter performance of an interconnect is important, especially for some wireline transmission applications that are used to link different parts of the system within a cabin or between the cabins. Performance evaluation can be accomplished by transient simulations using random pulse stream as a stimulus. The problem with the transient simulation is that many useful transmission line models operate in frequency domain and numerical integral transforms are required for transition to time domain. In this paper a method of estimating the jitter performance with simple operations on frequency domain data is proposed.

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Section: Theorymentioning

confidence: 98%

Estimation of the Interconnect Jitter Performance by Frequency Domain Behaviour

Tanskanen¹

2002

Proceedings: 6th IEEE Workshop on Signal Propagation on Interconnects

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“…First, Elmore delay is a reasonable measure of delay performance. As observed from experiments, Elmore delay is a good approximation of the half-value-point delay for a large class of RLC networks (Vlach et al 1991). Second, in contrast to the half-value-point delay, Elmore delay can be calculated analytically from the system transfer function.…”

Section: Introductionmentioning

confidence: 98%

“…One is the discovery that the Elmore delay is equivalent to the group delay at zero frequency (Vlach et al 1991). Thus, well-established theory and methods for group delay can be used for the analysis and sensitivity of Elmore delay.…”

Section: Introductionmentioning

confidence: 99%

Analysis, sensitivity and macromodelling of the Elmore delay in linear networks for performance-driven VLSI design

Shi

1993

International Journal of Electronics

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“…4) Even some large-signal behaviors, e.g., Elmore delay and other delay metrics for interconnect modeling of digital very large scale integrated (VLSI) circuits are related to the coefficients of the first few low-order terms [9], [28], [35]. 5) -expanded symbolic network functions may be advantageous for repetitive numerical evaluation.…”

Section: Introductionmentioning

confidence: 99%

Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design

Shi

Tan

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-A graph-based approach is presented for the generation of exact symbolic network functions in the form of rational polynomials of the complex frequency variable for analog integrated circuits. The approach employs determinant decision diagrams (DDDs) to represent the determinant of a circuit matrix and its cofactors. A notion of multiroot DDDs is introduced, where each root represents a symbolic expression for an individual coefficient of the powers of in the numerator and denominator of a network function, and multiple roots share their common subgraphs. A DDD-based algorithm is presented for generating -expanded network functions. We prove theoretically and validate experimentally that the algorithm constructs in ( DDD ) time an -expanded DDD with no more than DDD vertices, where is the degree of the denominator polynomial, is the maximum number of devices that connect to a circuit node, and DDD is the number of DDD vertices representing the circuit-matrix determinant. For a practical circuit, DDD is often many orders-ofmagnitude less than the number of product terms. In contrast, previous approaches require the time and space complexities proportional to the number of product terms, which grows exponentially with the size of a circuit. Experimental results have demonstrated that the new approach can produce exact -expanded-symbolic network functions for A741 operational amplifiers in several CPU seconds on an UltraSparc-I workstation. The expressive power of multiroot -expanded DDDs is so remarkable that in one instance, over 10 35 symbolic product terms have been represented by a multiroot DDD with less than 17 K vertices. The compactness of DDDs is further demonstrated in the context of symbolic noise evaluation, where potentially many transfer functions, each being used for a noise source in the circuit, can be represented by a single DDD with the size comparable to that for a few transfer functions. This provides a powerful tool for solving many symbolic analysis problems such as deriving interpretable symbolic expressions, dominant pole/zero estimation, and analog testability analysis. We have also demonstrated that repetitive numerical evaluation with the derived -expanded symbolic expressions for frequency-domain simulation and small-signal noise analysis can be much faster than SPICE-like simulators and the resulting expressions for a circuit block can be used as behavioral models for high-level simulation.

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Group delay as an estimate of delay in logic

Cited by 18 publications

References 6 publications

Estimation of the Interconnect Jitter Performance by Frequency Domain Behaviour

Estimation of the Interconnect Jitter Performance by Frequency Domain Behaviour

Analysis, sensitivity and macromodelling of the Elmore delay in linear networks for performance-driven VLSI design

Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design

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