Guarded dual rail logic for soft error tolerant standard cell library

Kaur, Raminder; Surana, Neelam; Mekie, Joycee

doi:10.1109/radecs.2016.8093144

Cited by 6 publications

(2 citation statements)

References 14 publications

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“…This is reliable but has high area, performance, and power penalties. Dual-mode and dualrail versions use two copies of the logic followed by a Muller C-element that waits until both copies agree before firing [8], [21] and are also costly. Alternatively, gates and storage elements can be sized to minimize the risk of soft-errors [10]- [12].…”

Section: Related Workmentioning

confidence: 99%

“…To circumvent the effects of these types of radiation, numerous Radiation Hardened by Design (RHBD) techniques have been proposed in the literature, the most common being the Triple Modular Redundancy (TMR) [7], Guarded Dual Modular Redundancy (GDMR) [8], gate sizing [9]- [12], and Glitch Filtering (GF) [13]- [15]. RHBD cell libraries have also been developed for both asynchronous and synchronous designs [16], [17].…”

Section: Introductionmentioning

confidence: 99%

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SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol

Aketi

Gupta

Cheng

et al. 2020

IEEE Trans. Circuits Syst. I

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The risk of soft errors due to radiation continues to be a significant challenge for engineers trying to build systems that can handle harsh environments. Building systems that are Radiation Hardened by Design (RHBD) is the preferred approach, but existing techniques are expensive in terms of performance, power, and/or area. This paper introduces a novel soft-error resilient asynchronous bundled-data design template, SERAD, which uses a combination of temporal and spatial redundancy to mitigate Single Event Transients (SETs) and upsets (SEUs). SERAD uses Error Detecting Logic (EDL) to detect SETs at the inputs of sequential elements and correct them via re-sampling. Because SERAD only pays the delay penalty in the presence of an SET, which rarely occurs, its average performance is comparable to the baseline synchronous design. We tested the SERAD design using a combination of Spice and Verilog simulations and evaluated its impact on area, frequency, and power on an open-core MIPS-like processor using a NCSU 45nm cell library. Our post-synthesis results show that the SERAD design consumes less than half of the area of the Triple Modular Redundancy (TMR), exhibits significantly less performance degradation than Glitch Filtering (GF), and consumes no more total power than the baseline unhardened design.

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