H-cluster: a hybrid architecture for three-dimensional many-core chips

Abstract

With more and more cores integrated in a single chip, threedimensional network-on-chip (3D NoC) based on through-silicon-via (TSV) is a good way to deal with the problem of large network diameter. But if the number of cores increase to several hundreds or even thousands, the large number of TSV cannot be neglected any more due to the low yield and high overhead of TSV. Therefore, it is necessary to obtain a balance point between cost and performance. In this letter, we propose H-cluster that applies a hybrid vertical interconnect scheme. It minimizes the number of TSV by sharing vertical links through vertical routers. The simulation results shows that the H-cluster can improve the yield of many-cores chip and provide a better performance.

Analysis and evaluation of noise coupling between through-silicon-vias

“…Three-dimensional stacked ICs (3D-SICs) with throughsilicon-vias are known as a solution to realize high-density multi chip module on a small footprint and has been started to be used in several high-performance electronics [1][2][3][4][5][6][7]. Through-silicon-vias (TSVs), the biggest feature of 3D-SICs, enable vertical signal transfer among stacked ICs which enhances performance and energy by optimized signal lines between stacked ICs [8][9][10][11][12][13]. Although wider signal bus is required for enormous scale data transfer, densely manufactured signal bus needs to solve crosstalk among the channels [14][15][16][17][18][19][20] as well as power line noise [21][22][23][24][25][26][27].…”