Half-coaxial-like transmission line using benzo cyclo butene layer

Kim, J.-M.; Cheon, Changyul; Kwon, Youngwoo; Kim, Y.-K.

doi:10.1049/el:20080973

Cited by 3 publications

(4 citation statements)

References 5 publications

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“…Those simulated and measured S 21 are 0.39 and 1.45 dB/cm at 20 GHz, respectively. The proposed hybrid SS shows TEM singlemode propagation up to 20 GHz, and also guarantees improved integration capability compared to the previous micromachined SS [5]. Conclusions: We propose the hybrid SS for broadband TEM singlemode propagation up to 20 GHz.…”

mentioning

confidence: 79%

Fabrication of hybrid shielded-stripline using half substrate integrated waveguide and half shielded-stripline structures

Bang

Kim

et al. 2011

Electron. Lett.

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A hybrid shielded-stripline (SS) for broadband TEM singlemode propagation up to 20 GHz is presented. Substrate integrated waveguide (SIW) technology is applied for designs of SS unhindered by the width and materials of the substrate. The hybrid structure, half SIW and half SS, which sandwich the buried-strip, is suggested for a simple fabrication. Therefore, the in-house vertical interconnection technique between two different planes on different substrates is proposed, which results in the realisation of the vias and the hybrid SS structures. The size of the hybrid SS, including transition, is 15.50 × 5.00 × 0.62 mm and the insertion loss is measured to be 1.45 dB/cm at 20 GHz.Introduction: A shielded-stripline (SS) is one of the planar type transmission lines for specific RF applications such as permittivity measurements (highly-sensitive-to-noise-systems) and security communications. It can implement TEM propagation, as well as high power and non-dispersive transmissions. A conventional SS consists of a buried-metal strip in the substrate (dielectric) which is surrounded by top and bottom GNDs, and metallic sidewalls. The surrounding GNDs screen the transmitted signal from external noise [1]. Its application, however, is still limited by complex fabrication and substrate design. Substrate integrated waveguide (SIW) technology can be applied to solve these difficulties and even offers a better integration capability by its planar nature. The SIW is synthesised by top and bottom GNDs surrounding the substrate with via-arrays. It shows similar field distribution to that of the rectangular waveguide [2]. Recently, an advanced study has proposed to propagate TEM waves by combining SIW with the conventional stripline, however, this still suffers from high cost and difficulties in fabrication owing to the via and multilayer structures [3].In this Letter, we propose the hybrid structured SS for a broadband TEM singlemode propagation using silicon micromachining and SIW technologies. The half SIW structure is applied to the design of SS for TEM singlemode propagation irrespective of the width and materials of the substrate up to 20 GHz. The in-house vertical interconnection technique, using sloped sidewalls, is suggested, which results in low-cost and simple fabrication for that multilayered structure and vias.

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mentioning

confidence: 79%

Fabrication of hybrid shielded-stripline using half substrate integrated waveguide and half shielded-stripline structures

Bang

Kim

et al. 2011

Electron. Lett.

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“…Previous studies ([4]- [6]) have shown that the use of high cost materials and process can reduce design environment uncertainty. However, most applications have different performance specifications, therefore, a package providing average performance is necessary in the market.…”

Section: Simulations and Measurements Of Test Patternsmentioning

confidence: 99%

“…In addition to satisfying high I/O requirements, the electrical performance is also an important item for wafer level packages. Although wafer level packaging technologies have been used for some time for low frequency analog and digital applications, they have recently been applied to packaging of components operating on very high frequency ranges with using BCB substrate and photolithography process [4]- [6]. In these previous studies, two items were found that could be improved.…”

Section: Introductionmentioning

confidence: 99%

Electrical evaluation of wafer level fan out (WLFO) package using organic substrates for microwave applications

Lee¹,

Kim²,

Kim³

et al. 2010

3rd Electronics System Integration Technology Conference ESTC

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In this paper, developments of wafer level fan-out (WLFO) technology using organic substrates, ajinomoto build-up film (ABF) with laser ablation process and buried pattern PCB, are introduced for low cost and high electrical performance not only on low frequency ranges but also microwave applications. WLFO technology using organic substrates can enhance routing density and provide smaller form factor than flip-chip chip scale packages (fcCSP). Moreover, short signal routing paths from die out to package out can be realized to improve overall electrical performance in WLFO, In this paper, the process of WLFO using ABF with laser drilling and buried-pattern PCB substrate are explained. In addition, measurements of coplanar waveguide (CPW) structure on WLFO and interconnection models from die I/O pad to balls using 3D EM simulation are conducted to estimate effectiveness in microwave ranges.

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“…Although wafer level packaging technologies have been used for some time for low-frequency analog and digital applications, they have recently been applied to packaging of millimeter wave components. With the recent progress of wafer process technologies, signals can be conducted at millimeter wave frequencies with low loss and flip-chip interconnects with benzocyclobutene (BCB) film substrate have shown excellent high frequency performance [7] [8] [9]. Two items were found in these previous studies that could be improved.. First, the metal thickness on BCB layer is very thin, 3um.…”

Section: Introductionmentioning

confidence: 99%

Electrical characterization of wafer level fan-out (WLFO) using film substrate for low cost millimeter wave application

Lee¹,

Kim²,

Karim³

et al. 2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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In this paper, development of wafer level fan-out (WLFO) technology using ajinomoto build-up film (ABF) substrate with laser ablation process is introduced for low cost and high electrical performance for millimeter wave application. Wafer level fan-out (WLFO) technology using ABF substrate can enhance routing density and provide smaller form factor with lower parasitic elements than flip-chip chip scale packages (FCCSP). Moreover, short electrical paths from die out to package out can be realized with WLFO, and the low-k ABF material provides good electrical properties for high frequency areas. In this paper, the process of WLFO using ABF substrate with laser drilling is explained and electrical parasitic elements are compared between FCCSP and WLFO using 3D simulation tools. In addition, electrical characterization of coplanar waveguide (CPW) structure and interconnection models from die I/O pad to balls using 3D EM simulation are conducted to estimate effectiveness on millimeter wave range. Actual measurements of CPW structures are also presented.

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Half-coaxial-like transmission line using benzo cyclo butene layer

Cited by 3 publications

References 5 publications

Fabrication of hybrid shielded-stripline using half substrate integrated waveguide and half shielded-stripline structures

Fabrication of hybrid shielded-stripline using half substrate integrated waveguide and half shielded-stripline structures

Electrical evaluation of wafer level fan out (WLFO) package using organic substrates for microwave applications

Electrical characterization of wafer level fan-out (WLFO) using film substrate for low cost millimeter wave application

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