2002
DOI: 10.1063/1.1478779
|View full text |Cite
|
Sign up to set email alerts
|

Hall mobility enhancement caused by annealing of Si0.2Ge0.8/Si0.7Ge0.3/Si(001) p-type modulation-doped heterostructures

Abstract: The effect of post-growth furnace thermal annealing (FTA) on the Hall mobility and sheet carrier density measured at 9–300 K in the Si0.2Ge0.8/Si0.7Ge0.3/Si(001) p-type modulation-doped heterostructures was studied. FTA treatments in the temperature range of 600–900 °C for 30 min were performed on similar heterostructures but with two Si0.2Ge0.8 channel thicknesses. The annealing at 600 °C is seen to have a negligible effect on the Hall mobility as well as on the sheet carrier density. Increases in the anneali… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
4
0

Year Published

2004
2004
2019
2019

Publication Types

Select...
8

Relationship

0
8

Authors

Journals

citations
Cited by 13 publications
(4 citation statements)
references
References 8 publications
0
4
0
Order By: Relevance
“…The decrease became slightly steeper above ϳ60 K. For the 2.5-nm-thick QW sample, the mobility increases up to a temperature of 60 K. Figure 3 summarizes the mobility at 8 K as a function of QW thickness L. The highest of 0.44 m 2 /V s obtained for the 7-nm-thick sample at 8 K is larger than the recently reported value of 0.062 m 2 /V s for a 10-nm-thick Si 0.2 Ge 0.8 QW grown at 300°C on Si 0.8 Ge 0.3 virtual substrates. 9 The factor 7 higher mobility of our sample reflects the small roughness of the substrates and the small thickness fluctuation of our samples. When L is increased from 2.5 to 4.5 nm, increases steeply.…”
mentioning
confidence: 83%
“…The decrease became slightly steeper above ϳ60 K. For the 2.5-nm-thick QW sample, the mobility increases up to a temperature of 60 K. Figure 3 summarizes the mobility at 8 K as a function of QW thickness L. The highest of 0.44 m 2 /V s obtained for the 7-nm-thick sample at 8 K is larger than the recently reported value of 0.062 m 2 /V s for a 10-nm-thick Si 0.2 Ge 0.8 QW grown at 300°C on Si 0.8 Ge 0.3 virtual substrates. 9 The factor 7 higher mobility of our sample reflects the small roughness of the substrates and the small thickness fluctuation of our samples. When L is increased from 2.5 to 4.5 nm, increases steeply.…”
mentioning
confidence: 83%
“…A 4.2 K mobility of 87 000 cm 2 V Ϫ1 s Ϫ1 ͑at 6.2ϫ10 11 cm Ϫ2 ) has already been reported 1 and roomtemperature mobilities of around 3000 cm 2 V Ϫ1 s Ϫ1 have been found using mobility spectrum analysis. [1][2][3] Some of the physical properties of holes in strained Ge have been studied. 4 -7 Here, we analyze the sheet density dependence of the mobility in high-mobility material.…”
mentioning
confidence: 99%
“…As x −y = 0.3 in both structures the strain in the p-channel will be the same. The PMOSFET devices were fabricated using reduced thermal budget processing at 650 • C, to minimize Ge out-diffusion from the strained Si 1−x Ge x channel [7] and to avoid Sb penetration to the channel, with 200 nm of plasma enhanced CVD (PECVD) SiO 2 deposited as a field oxide. In the active transistor area the field oxide was removed by wet chemical etching.…”
Section: Mosfet Fabricationmentioning
confidence: 99%