HALT evaluation of SJ BIST technology for electronic prognostics

Hofmeister, James; Vohnout, Sonia; Mitchell, Christopher; Heimes, Felix O.; Saha, Sagnik

doi:10.1109/autest.2010.5613585

Cited by 7 publications

(6 citation statements)

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“…Several methods have been used traditionally for testing interconnects at the board level such as DC resistance measurements, 6 radio-frequency (RF) impedance analysis 7,8 Built-in Self-Test (BIST) 9 and analog neural network technology. 10 DC resistance measurements 6 is a useful method to detect stuck-at short, stuck-at open and bridge faults in interconnections at test mode.…”

Section: Related Workmentioning

confidence: 99%

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A Digital On-Line Monitor for Detecting Intermittent Resistance Faults at Board Level

Ebrahimi

Kerkhoff

2019

J CIRCUIT SYST COMP

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The reliability of board-level data communications intensively depends on the reliability of interconnections on a board. One of the most challenging interconnections reliability threats is intermittent resistive faults (IRFs). Detecting such faults is a major challenge. The main reason is the random behavior of these faults. They may occur randomly in time, duration and amplitude. The occurrence rate can vary from a few nanoseconds to months. This paper investigates IRF detection at the board level by introducing a new digital in situ IRF monitor. Hardware-based fault injection has been used to validate the proposed IRF monitor. As case studies, two widely used on-board transmission protocols namely the Universal Asynchronous Receiver Transmitter (UART) and the Serial Peripheral Interface bus (SPI), have been used. In addition, one fault management framework, based on the IJTAG standard, has been implemented to collect and characterize information from the monitors. The experimental results show that the proposed monitor is effective in detecting IRFs at the board level.

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Section: Related Workmentioning

confidence: 99%

“…A method based on BIST, referred to as SJ BIT, was proposed in Ref. 9. It can detect faults induced by solder-joint fractures in the input/output pins of¯eld programmable gate array (FPGA) devices.…”

Section: To Monitor Degradation In Connectorsmentioning

confidence: 99%

A Digital On-Line Monitor for Detecting Intermittent Resistance Faults at Board Level

Ebrahimi

Kerkhoff

2019

J CIRCUIT SYST COMP

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“…This method provides potential failure modes for each system component, and potential failure modes for each component are extracted based on the physics of failure. Hofmeister et al (2010) proposed a diagnostics and prognostics tool for field programmable gate array (FPGA) devices and used HALT to confirm the validity of the tool. The four FPGA boards were assessed to identify failures due to thermal cycling and vibration stresses.…”

Section: Introductionmentioning

confidence: 99%

Prognostics in Highly Accelerated Limit Testing Using Deep Learning Data Analysis

Shibutani

2023

PHMAP_CONF

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In this study, an anomaly detection analysis of electronic components was conducted using deep learning algorithms on time-series data of voltage monitored during highly accelerated limit testing (HALT) on inverters used in automobiles and other vehicles. We demonstrated that the anomaly detection technology of time-series data using deep learning could detect equipment anomalies/failures to achieve effective data representation, improving the reliability assurance technology with HALT.

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“…Unstable and defected interconnections are the primary source of IRFs at the board level. Several methods have been used traditionally for testing interconnections at the board level, such as DC resistance measurements [Pan14], radio-frequency (RF) impedance analysis [Kwo11], [Loe12], Built-in Self-Test [Hof10] and analogue neural network technology [Ste08]. DC resistance measurements [Pan14] is a valuable method to detect stuck-at-short, stuck-at-open and bridge faults in interconnections at test mode.…”

Section: Intermittent Fault Detection At Board Levelmentioning

confidence: 99%

“…Another technique to test interconnection reliability at the board level is based on BIST. A method based on BIST, referred to as SJ BIST, was proposed in [Hof10]. It can detect faults induced by solder-joint fractures in the input/output pins of field-programmable gate array (FPGA) devices.…”

Section: Intermittent Fault Detection At Board Levelmentioning

confidence: 99%

Design and verification of embedded instruments for detecting intermittent resistive faults in electronic systems

Ebrahimi¹

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HALT evaluation of SJ BIST technology for electronic prognostics

Cited by 7 publications

References 0 publications

A Digital On-Line Monitor for Detecting Intermittent Resistance Faults at Board Level

A Digital On-Line Monitor for Detecting Intermittent Resistance Faults at Board Level

Prognostics in Highly Accelerated Limit Testing Using Deep Learning Data Analysis

Design and verification of embedded instruments for detecting intermittent resistive faults in electronic systems

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