Proceedings of the 59th ACM/IEEE Design Automation Conference 2022
DOI: 10.1145/3489517.3530672
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Hammer

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Cited by 15 publications
(1 citation statement)
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“…We partition each SoC into about 10 ∼ 50 chiplets based on their functions and build a chiplet pool consisting of about 300 chiplets. We use Hammer [31] tools with 7-nm standard cell library ASAP7 [32] to synthesize various SoC designs and obtain the area information of each chiplet, which guides the floorplan optimization.…”
Section: A Benchmarks and Baselinementioning
confidence: 99%
“…We partition each SoC into about 10 ∼ 50 chiplets based on their functions and build a chiplet pool consisting of about 300 chiplets. We use Hammer [31] tools with 7-nm standard cell library ASAP7 [32] to synthesize various SoC designs and obtain the area information of each chiplet, which guides the floorplan optimization.…”
Section: A Benchmarks and Baselinementioning
confidence: 99%