Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip

Zhang, Guangda; Song, Wei; Garside, Jim; Navaridas, Javier; Wang, Zhiying

doi:10.1109/tvlsi.2017.2729081

Cited by 5 publications

(1 citation statement)

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“…On the other hand, [ 31 , 32 ] conducted different studies to enhance circuit performance. In addition, some studies focused on analyzing the reliability of delay-insensitive circuits; the authors of [ 33 ] systematically investigated the impact of permanent faults on the QDI NOC (quasi-delay-insensitive networks-on-chip) and proposed new detection and recovery techniques. The application of delay-insensitive coding in high-speed packaged interconnects can effectively increase the interconnect performance and reduce the wiring spacing of interconnects due to its high crosstalk immunity, which is essential for simplifying the design of interconnects.…”

Section: Introductionmentioning

confidence: 99%

Crosstalk Analysis of Delay-Insensitive Code in High-Speed Package Interconnects

Sun

2023

Micromachines

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The development of integrated circuits has increased the size of chip interconnects, which has brought challenges to interconnect design in chip packages. The closer the spacing between interconnects, the higher the space utilization, which can cause severe crosstalk problems in high-speed circuits. In this paper, we applied delay-insensitive coding to the design of high-speed package interconnects. We also analyzed the effect of delay-insensitive coding on crosstalk improvement in package interconnects at 26 GHz for its high crosstalk immunity. Compared to the synchronous transmission circuit, the 1-of-2 and 1-of-4 encoded circuits designed in this paper can reduce crosstalk peaks by 22.9% and 17.5% on average at a wiring spacing of 1–7 μm, which can achieve closer wiring spacing.

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Section: Introductionmentioning

confidence: 99%