Handling stuck-at-faults in memristor crossbar arrays using matrix transformations

Zhang, Baogang; Uysal, Necati; Fan, Deliang; Ewetz, Rickard

doi:10.1145/3287624.3287707

Cited by 35 publications

(26 citation statements)

References 15 publications

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“…For instance, some works address the problem from a logical/functional perspective, modelling the forward pass in each of the synaptic layers of the DNN simply as a mathematical matrix product between a vector of voltages and a matrix of conductances, which results in a vector of currents. This is the case for the works reported by Zhang et al [55,56] (2019), simulated in C++ and MATLAB. Although such a CPA modelling and simulation platform allows one to deal with large fully connected (FC) and convolutional neural networks (CNNs) (and even more complex ANN architectures, such as the modified VGG-11 comprising 7.66 × 10 6 synapses considered in the work of Xia et al [26] (2017)), this approach is incapable of accounting for the electrical equivalent of the memristor-based CPA.…”

Section: Simulation Platformmentioning

confidence: 81%

“…In the most unrealistic scenario, RRAM devices are modeled as a resistor of fixed value, which imposes a variety of limitations, perhaps the most important being: (i) such modelling is not capable of capturing the non-linearity of the RRAM devices (especially in the HRS regime), which may result in the under/overestimation of the device current [28]; (ii) it does not account for the SET/RESET transitions. This is the case for the works by Zhang et al [55,56] (2019), Xia et al [22,26] (2017 and 2018), Woo et al [57] (2020), and Yeo et al [59] (2019). As previously mentioned, given these boundary conditions, the most suitable simulation platform is SPICE.…”

Section: Rram Modelsmentioning

confidence: 83%

“…However, this is not valid for large CPAs or highly scaled metallic lines [27] (due to the size-dependent resistivity of Cu [50][51][52]), as the effects of the IR drops become notorious for the cells located away from the input terminals, resulting in a significant reduction of the voltage delivered to the cells located away from the input/output terminals. To the best of our knowledge, this is a limitation in the works of Mehonic et al [53] (from 2019), Dias et al [54] (2015), Zhang et al [55,56] (2019), Xia et al [22,26] (2017 and 2018), Woo et al [57] (2020), Huang et al [58] (2021), Yeo et al [59] (2019), and Van Pham et al [60] (2019).…”

Section: Cpa Modellingmentioning

confidence: 95%

“…However, most importantly, the repeated write cycles of the RRAM devices during the training loops also generate a new threat to the device endurance. Four additional works (Zhang et al [55,56] (2019) and Xia et al [22,26] (2017) and ( 2018)) discuss SAF mitigation techniques, but provide oversimplified CPA and memristor modelling approaches. Finally, another two works (Liu et al [24] (2015) and Chen et al [61] (2017)) tested mitigation techniques over a hardware CPA as a test vehicle.…”

Section: Costs Associated With the Mitigation Of Saf Effectsmentioning

confidence: 99%

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Assessment and Improvement of the Pattern Recognition Performance of Memdiode-Based Cross-Point Arrays with Randomly Distributed Stuck-at-Faults

et al. 2021

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In this work, the effect of randomly distributed stuck-at faults (SAFs) in memristive cross-point array (CPA)-based single and multi-layer perceptrons (SLPs and MLPs, respectively) intended for pattern recognition tasks is investigated by means of realistic SPICE simulations. The quasi-static memdiode model (QMM) is considered here for the modelling of the synaptic weights implemented with memristors. Following the standard memristive approach, the QMM comprises two coupled equations, one for the electron transport based on the double-diode equation with a single series resistance and a second equation for the internal memory state of the device based on the so-called logistic hysteron. By modifying the state parameter in the current-voltage characteristic, SAFs of different severeness are simulated and the final outcome is analysed. Supervised ex-situ training and two well-known image datasets involving hand-written digits and human faces are employed to assess the inference accuracy of the SLP as a function of the faulty device ratio. The roles played by the memristor’s electrical parameters, line resistance, mapping strategy, image pixelation, and fault type (stuck-at-ON or stuck-at-OFF) on the CPA performance are statistically analysed following a Monte-Carlo approach. Three different re-mapping schemes to help mitigate the effect of the SAFs in the SLP inference phase are thoroughly investigated.

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Section: Simulation Platformmentioning

confidence: 81%

Section: Rram Modelsmentioning

confidence: 83%

Section: Cpa Modellingmentioning

confidence: 95%

Section: Costs Associated With the Mitigation Of Saf Effectsmentioning

confidence: 99%

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Assessment and Improvement of the Pattern Recognition Performance of Memdiode-Based Cross-Point Arrays with Randomly Distributed Stuck-at-Faults

et al. 2021

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“…Thus it is hard to directly perform fix against the SA0 cell. We employ the row flipping transformation method proposed by B. Zhang et al [30] to change SA0 errors to SA1 errors effectively. Hence we propose a software and hardware co-design method to reduce the effect of SAF:…”

Section: Resultsmentioning

confidence: 99%

Current injection: a hardware method of adapting non-ideal effects of ReRAM based deep learning accelerator

Liu

Zhang³

et al. 2020

IEICE Electron. Express

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Non-ideal effects of ReRAM are the major limitations of deploying crossbar based neural network accelerator in the real world. Noise injection could effectively mitigate the non-ideal effects because it is equivalent to an adaptive regularization to the neural network. However, software-based noise injection involves computation-hungry retraining and data extraction. In this paper, we propose a ReRAM crossbar based neural network accelerator with current injection to adapt non-ideal effects in the ReRAM crossbar. We inject current into the crossbar through randomly set ReRAM cells to add the adaptive regularization, and no retraining and data extraction is needed in our proposal. We evaluate our method on three neural networks: LeNet-5, ResNet-20 and ResNet-50. Results show that current injection can reduce the accuracy degradation due to Stuck at Fault (SAF) and IR drop to 1%, and 5%, respectively.

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Memristive, Spintronic, and 2D‐Materials‐Based Devices to Improve and Complement Computing Hardware

Joksas

AlMutairi

Lee

et al. 2022

Advanced Intelligent Systems

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In a data-driven economy, virtually all industries benefit from advances in information technology-powerful computing systems are critically important for rapid technological progress. However, this progress might be at risk of slowing down if the discrepancy between the current computing power demands and what the existing technologies can offer is not addressed. Key limitations to improving energy efficiency are the excessive growth of data transfer costs associated with the von Neumann architecture and the fundamental limits of complementary metal-oxide-semiconductor (CMOS) technologies, such as transistors. Herein, three approaches that will likely play an essential role in future computing systems are discussed: memristive electronics, spintronics, and electronics based on 2D materials. The authors present how these technologies may transform conventional digital computers and contribute to the adoption of new paradigms, like neuromorphic computing.

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Handling stuck-at-faults in memristor crossbar arrays using matrix transformations

Cited by 35 publications

References 15 publications

Assessment and Improvement of the Pattern Recognition Performance of Memdiode-Based Cross-Point Arrays with Randomly Distributed Stuck-at-Faults

Assessment and Improvement of the Pattern Recognition Performance of Memdiode-Based Cross-Point Arrays with Randomly Distributed Stuck-at-Faults

Current injection: a hardware method of adapting non-ideal effects of ReRAM based deep learning accelerator

Memristive, Spintronic, and 2D‐Materials‐Based Devices to Improve and Complement Computing Hardware

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