2024
DOI: 10.55041/ijsrem35738
|View full text |Cite
|
Sign up to set email alerts
|

Hardware Accelerated AES: RTL to GDS

Rakshan Kulkarni

Abstract: This paper presents a hardware-accelerated Advanced Encryption Standard (AES) implementation featuring an 11-stage pipelined architecture and an optimized subkey generation scheme for enhanced performance. This design is implemented in Verilog and verified through waveform analysis. Operating at a maximum clock frequency of 100 MHz, our implementation achieves significant efficiency. The final design occupies an area of 1.44 mm2 and consists of 32,424 standard cells, with a power consumption of 32 mW at the ty… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Publication Types

Select...

Relationship

0
0

Authors

Journals

citations
Cited by 0 publications
references
References 13 publications
0
0
0
Order By: Relevance

No citations

Set email alert for when this publication receives citations?