Hardware-Accelerated Hypergraph Processing with Chain-Driven Scheduling

PhGraph: A High-Performance ReRAM-Based Accelerator for Hypergraph Applications

“…A hypergraph is typically represented in the bipartite representation format [2], [7], [8], which represents each hyperedge as a distinct vertex and connects the vertex with its incident vertices. Thus, as shown in Fig.…”

“…Thus, as shown in Fig. 1c, a hypergraph can be represented as a bipartite graph and stored with an extended CSR format [7]. In addition, a hypergraph can also be represented as an incidence matrix, as shown in Fig.…”

“…Similarly, the latter utilizes the newly activated hyperedges to update vertices using a vertex update function. Previous studies [7], [8] have shown that hypergraph processing is typically memory-bound. Recent solutions, based on CPUs [1] and ASICs [7], [8], improve the locality of hypergraph processing by exploiting the intrinsic hypergraph structure overlap.…”

“…Previous studies [7], [8] have shown that hypergraph processing is typically memory-bound. Recent solutions, based on CPUs [1] and ASICs [7], [8], improve the locality of hypergraph processing by exploiting the intrinsic hypergraph structure overlap. However, they remain inadequate in addressing the memory bottleneck arising in hypergraph processing.…”

“…On the other hand, the existing ReRAM-based graph processing accelerator family, in order to harness the massive parallelism provided by the matrix-structured crossbar architecture, has to hold an assumption that crossbar cells are fully utilized [9], [10]. However, real-world hypergraph structure is often overlapped in the sense that the majority of vertices are associated with at least two hyperedges, and vice versa [7]. Thus, hypergraph processing exhibits overlap-induced workload irregularity.…”