Hardware Acceleration and Implementation of YOLOX-s for On-Orbit FPGA

Abstract

The rapid development of remote sensing technology has brought about a sharp increase in the amount of remote sensing image data. However, due to the satellite’s limited hardware resources, space, and power consumption constraints, it is difficult to process massive remote sensing images efficiently and robustly using the traditional remote sensing image processing methods. Additionally, the task of satellite-to-ground target detection has higher requirements for speed and accuracy under the conditions of more and more remote sensing data. To solve these problems, this paper proposes an extremely efficient and reliable acceleration architecture for forward inference of the YOLOX-s detection network an on-orbit FPGA. Considering the limited onboard resources, the design strategy of the parallel loop unrolling of the input channels and output channels is adopted to build the largest DSP computing array to ensure a reliable and full utilization of the limited computing resources, thus reducing the inference delay of the entire network. Meanwhile, a three-path cache queue and a small-scale cascaded pooling array are designed, which maximize the reuse of on-chip cache data, effectively reduce the bandwidth bottleneck of the external memory, and ensure an efficient computing of the entire computing array. The experimental results show that at the 200 MHz operating frequency of the VC709, the overall inference performance of the FPGA acceleration can reach 399.62 GOPS, the peak performance can reach 408.4 GOPS, and the overall computing efficiency of the DSP array can reach 97.56%. Compared with the previous work, our architecture design further improves the computing efficiency under limited hardware resources.

Puppis: Hardware Accelerator of Single-Shot Multibox Detectors for Edge-Based Applications

“…The Control module guides the NMS module through Listing 2. The core of that algorithm is Equations ( 10)- (16). Figure 10 shows an abstract RTL schematic of the NMS module.…”

“…During its operation, for all multiplication operations, this module utilizes the Muls block. For all boxes, except the first one, the module calculates O from Equation (16). The Divider block is employed when division is required, and the module obtains the O value through the dib_in port.…”

“…While there are numerous proposals for algorithmic improvements of the original SSD algorithm available, despite existing proposals for the hardware acceleration of other object detection architectures [16][17][18][19], there are not many proposals for the hardware acceleration of a single-shot multibox detector algorithm in the available literature. The authors are aware of only two previously published papers [20,21], who presented the acceleration of the convolutional blocks within the SSD network, without focusing on the SSD postprocessing part of the network.…”

Improved YOLOv7 Algorithm for Small Object Detection in Unmanned Aerial Vehicle Image Scenarios

“…Memory is tasked with both storing image data and facilitating temporary transfers. The data bus is responsible for transmitting pixel data, and the bandwidth affects the transmission of image data at the same time [15]. These existing problems make object detection in UAV images a significant challenge in practical applications.…”