Hardware acceleration for object detection using YOLOv4 algorithm on Xilinx Zynq platform

Babu, Praveenkumar; Parthasarathy, Eswaran

doi:10.1007/s11554-022-01234-y

Cited by 9 publications

(5 citation statements)

References 32 publications

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“…However, they also exhibit some reduction in accuracy. They are deployed on FPGA-based embedded computing platforms and have achieved better real-time detection results, utilizing architectures with high performance and low energy consumption [30][31][32].…”

Section: Related Work and Motivationmentioning

confidence: 99%

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High-Speed CNN Accelerator SoC Design Based on a Flexible Diagonal Cyclic Array

Lee,

Aliev,

Junaid

et al. 2024

Electronics

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The latest convolutional neural network (CNN) models for object detection include complex layered connections to process inference data. Each layer utilizes different types of kernel modes, so the hardware needs to support all kernel modes at an optimized speed. In this paper, we propose a high-speed and optimized CNN accelerator with flexible diagonal cyclic arrays (FDCA) that supports the acceleration of CNN networks with various kernel sizes and significantly reduces the time required for inference processing. The accelerator uses four FDCAs to simultaneously calculate 16 input channels and 8 output channels. Each FDCA features a 4 × 8 systolic array that contains a 3 × 3 processing element (PE) array and is designed to handle the most commonly used kernel sizes. To evaluate the proposed CNN accelerator, we mapped the widely used YOLOv5 CNN model and evaluated the performance of its implementation on the Zynq UltraScale+ MPSoC ZCU102 FPGA. The design consumes 249,357 logic cells, 2304 DSP blocks, and only 567 KB BRAM. In our evaluation, the YOLOv5n model achieves an accuracy of 43.1% (mAP@0.5). A prototype accelerator has been implemented using Samsung’s 14 nm CMOS technology. It achieves 1.075 TOPS, a peak performance with a 400 MHz clock frequency.

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Section: Related Work and Motivationmentioning

confidence: 99%

“…The accelerators have been configured to run Tiny-YOLOv3 [30] and Tiny-YOLOv4 [32] in real time, achieving performance of over 8.3 and 30 frames per second.…”

Section: Related Work and Motivationmentioning

confidence: 99%

High-Speed CNN Accelerator SoC Design Based on a Flexible Diagonal Cyclic Array

Lee,

Aliev,

Junaid

et al. 2024

Electronics

View full text Add to dashboard Cite

show abstract

“…Thus, alternative hardware solutions and optimization techniques are needed to ensure that the power consumption of the embedded CNNs remains within acceptable limits while meeting the performance requirements of ADAS. In particular, an optimized version of YOLOv4 has been proposed by [11], which presents hardware acceleration of the YOLOv4 object detection algorithm on the Xilinx Zynq-7000 system-on-chip (SoC). The proposed implementation enables efficient resource utilization of 43.6% of LUTs, 43.04% of Flip-flops, 82.17% of BRAMs, 79% of DSPs, 189.14 GOP/s throughput, and 10.36 W power consumption.…”

Section: Related Workmentioning

confidence: 99%

Efficient GEMM Implementation for Vision-Based Object Detection in Autonomous Driving Applications

Guerrouj

Rodríguez

Abouzahir³

et al. 2023

JLPEA

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Convolutional Neural Networks (CNNs) have been incredibly effective for object detection tasks. YOLOv4 is a state-of-the-art object detection algorithm designed for embedded systems. It is based on YOLOv3 and has improved accuracy, speed, and robustness. However, deploying CNNs on embedded systems such as Field Programmable Gate Arrays (FPGAs) is difficult due to their limited resources. To address this issue, FPGA-based CNN architectures have been developed to improve the resource utilization of CNNs, resulting in improved accuracy and speed. This paper examines the use of General Matrix Multiplication Operations (GEMM) to accelerate the execution of YOLOv4 on embedded systems. It reviews the most recent GEMM implementations and evaluates their accuracy and robustness. It also discusses the challenges of deploying YOLOv4 on autonomous vehicle datasets. Finally, the paper presents a case study demonstrating the successful implementation of YOLOv4 on an Intel Arria 10 embedded system using GEMM.

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“…Therefore, the HDL coder allows for the functional testing of several image processing methods and fast synthesis of many more, including custom filtering, colorspace conversion, picture statistics gathering, and many more. But there isn't currently any visible support for image segmentation tasks in the toolbox version [12].…”

Section: Introductionmentioning

confidence: 99%

Efficient Real time Zynq 7000 FPGA deployment of optimized YOLOv2 deep leaning model for target detection, based on HDL Coder Methodology

Slimane

2024

IJITS

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Field Programmable Gate Arrays (FPGAs) have garnered significant attention in the development and enhancement of target identification algorithms that employ YOLOv2 models and FPGAs, owing to their adaptability and user-friendliness. The Simulink HDL compiler was utilized to design, simulate, and implement our proposed design. In an effort to rectify this, this paper presents a comprehensive programming and design proposal. The implementation of the YOLOv2 algorithm for real-time vehicle detection on the Xilinx® Zynq-7000 System-on-a-chip is proposed in this work. Real-time testing of the synthesised hardware revealed that it can process Full HD video at a rate of 16 frames per second. On the Xilinx Zynq-7000 SOC, the estimated dynamic power consumption is less than 90 mW. When comparing the results of the proposed work to those of other simulations, it is observed that resource utilization is enhanced by around 204 k (75%) LUT, 305 (12%) DSP, and 224 k (41%) flip-flops at 200 MHz.

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Hardware acceleration for object detection using YOLOv4 algorithm on Xilinx Zynq platform

Cited by 9 publications

References 32 publications

High-Speed CNN Accelerator SoC Design Based on a Flexible Diagonal Cyclic Array

High-Speed CNN Accelerator SoC Design Based on a Flexible Diagonal Cyclic Array

Efficient GEMM Implementation for Vision-Based Object Detection in Autonomous Driving Applications

Efficient Real time Zynq 7000 FPGA deployment of optimized YOLOv2 deep leaning model for target detection, based on HDL Coder Methodology

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