Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration

Abstract

In this paper, a high-sensitivity low-cost power-aware Support Vector Machine (SVM) training and classification based system, is hardware implemented for a neural seizure detection application. The training accelerator algorithm, adopted in this work, is the sequential minimal optimization (SMO). System blocks are implemented to achieve the best trade-off between sensitivity and the consumption of area and power. The proposed seizure detection system achieves 98.38% sensitivity when tested with the implemented linear kernel classifier. The system is implemented on different platforms: such as Field Programmable Gate Array (FPGA) Xilinx Virtex-7 board and Application Specific Integrated Circuit (ASIC) using hardwarecalibrated UMC 65nm CMOS technology. A power consumption evaluation is performed on both the ASIC and FPGA platforms showing that the ASIC power consumption is lower by at least 65% when compared with the FPGA counterpart. A power-aware system is implemented with FPGAs by the adoption of the Dynamic Partial Reconfiguration (DPR) technique that allows the dynamic operation of the system based on power level available to the system at the expense of degradation of the system accuracy. The proposed system exploits the advantages of DPR technology in FPGAs to switch between two proposed designs providing a decrease of 64% in power consumption.

Automatic Detection and Classification of Epileptic Seizures from EEG Data: Finding Optimal Acquisition Settings and Testing Interpretable Machine Learning Approach

“…Other researchers established that the higher sampling frequency of scalp EEG also did not boost seizure detection. In their study, Acc, Sn and Sp differed by 1–2% for the SR values of 256, 512 and 1024 Hz [ 72 ]. In analogy to this, the rising acquisition frequency of the intracranial EEG improved neither detection of the seizure onset nor localization of epileptogenic foci [ 73 ].…”

Agile FPGA Computing at the 5G Edge: Joint Management of Accelerated and Software Functions for Open Radio Access Technologies

“…These efforts are valuable to increase the availability of FPGAs to virtual machines or containers and to enhance the flexibility of cloud FPGA deployments [16,17]. The value of FPGA computing with PR is also manifested by its adoption in different vertical sector use cases [18][19][20][21]. One of the latest research interests is to use FPGA computing and PR in those use cases where ML models need to be deployed and reconfigured on the fly [22,23].…”

CNN inference acceleration on limited resources FPGA platforms_epilepsy detection case study

“…In terms of power consumption, the proposed approach outperforms state-of-the-art work by a factor of 6. Elhosary et al [5] proposed a seizure detection system based on a support vector machine (SVM) classifier. The system is implemented and evaluated on two different platforms: field programmable gate array (FPGA) (Xilinx Virtex-7 board) and application-specific integrated circuit (ASIC) (UMC 65 nm CMOS technology).…”