Hardware acceleration of MUSIC based DoA estimator in MUBTS

Yan, Jing; Huang, Yifeng; Xu, Hantao; Vandenbosch, Guy A. E.

doi:10.1109/eucap.2014.6902343

Cited by 21 publications

(17 citation statements)

References 5 publications

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“…Regarding the hardware design efficiency of the proposed work, our literature survey cannot identify any other work with chip design. However, there have been works [28][29][30][31] with hardware implementations reported in recent years and all of them are using the FPGA technology. In industry practices, FPGA is usually employed in the cases of system prototyping or when product volume is not large enough to economically justify the Application Specific Integrated Circuit (ASIC) implementation.…”

Section: Comparison With Other Doa Hardware Implementation Workmentioning

confidence: 99%

“…From Table 6, design [29] and the proposed work target a 1 × 8 antenna array while the remaining four use a 1 × 4 antenna array. This means the problem complexity of a 1 × 4 antenna array is roughly one eighth that of a 1×8 antenna array.…”

Section: Comparison With Other Doa Hardware Implementation Workmentioning

confidence: 99%

“…FPGA, because of its programmable feature and a lot of logic overhead, can barely meet the speed achieved by ASIC. The hardware complexity, although listed in the comparison table, is not compared because there is no From Table 6, design [29] and the proposed work target a 1 × 8 antenna array while the remaining four use a 1 × 4 antenna array. This means the problem complexity of a 1 × 4 antenna array is roughly one eighth that of a 1×8 antenna array.…”

Section: Comparison With Other Doa Hardware Implementation Workmentioning

confidence: 99%

“…Except for design [29], all other designs have successfully confined their initiation intervals to less than 4 µs. Design [29] uses relatively fewer FPGA resources than other FPGA based design. It also deals with a 1 × 8 rather than a 1 × 4 antenna array.…”

Section: Comparison With Other Doa Hardware Implementation Workmentioning

confidence: 99%

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A Low Complexity, High Throughput DoA Estimation Chip Design for Adaptive Beamforming

Chen

Ma²,

Hwang

et al. 2020

Electronics

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Direction of Arrival (DoA) estimation is essential to adaptive beamforming widely used in many radar and wireless communication systems. Although many estimation algorithms have been investigated, most of them focus on the performance enhancement aspect but overlook the computing complexity or the hardware implementation issues. In this paper, a low-complexity yet effective DoA estimation algorithm and the corresponding hardware accelerator chip design are presented. The proposed algorithm features a combination of signal sub-space projection and parallel matching pursuit techniques, i.e., applying signal projection first before performing matching pursuit from a codebook. This measure helps minimize the interference from noise sub-space and makes the matching process free of extra orthogonalization computations. The computing complexity can thus be reduced significantly. In addition, estimations of all signal sources can be performed in parallel without going through a successive update process. To facilitate an efficient hardware implementation, the computing scheme of the estimation algorithm is also optimized. The most critical part of the algorithm, i.e., calculating the projection matrix, is largely simplified and neatly accomplished by using QR decomposition. In addition, the proposed scheme supports parallel matches of all signal sources from a beamforming codebook to improve the processing throughput. The algorithm complexity analysis shows that the proposed scheme outperforms other well-known estimation algorithms significantly under various system configurations. The performance simulation results further reveal that, subject to a beamforming codebook with a 5° angular resolution, the Root Mean Square (RMS) error of angle estimations is only 0.76° when Signal to Noise Ratio (SNR) = 20 dB. The estimation accuracy outpaces other matching pursuit based approaches and is close to that of the classic Estimation of Signal Parameters Via Rotational Invariance Techniques (ESPRIT) scheme but requires only one fifth of its computing complexity. In developing the hardware accelerator design, pipelined Coordinate Rotation Digital Computer (CORDIC) processors consisting of simple adders and shifters are employed to implement the basic trigonometric operations needed in QR decomposition. A systolic array architecture is developed as the computing kernel for QR decomposition. Other computing modules are also realized using various linear systolic arrays and chained together seamlessly to maximize the computing throughput. A Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm CMOS process was chosen as the implementation technology. The gate count of the chip design is 454.4k, featuring a core size of 0.76 mm 2 , and can operate up to 333 MHz. This suggests that one DoA estimation, with up to three signal sources, can be performed every 2.38 μs.

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Section: Comparison With Other Doa Hardware Implementation Workmentioning

confidence: 99%

Section: Comparison With Other Doa Hardware Implementation Workmentioning

confidence: 99%

Section: Comparison With Other Doa Hardware Implementation Workmentioning

confidence: 99%

Section: Comparison With Other Doa Hardware Implementation Workmentioning

confidence: 99%

See 2 more Smart Citations

A Low Complexity, High Throughput DoA Estimation Chip Design for Adaptive Beamforming

Chen

Ma²,

Hwang

et al. 2020

Electronics

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“…Among those processors, reconfigurable computing [12][13][14] is becoming more promising because reconfigurable architectures are flexible, scalable, and provide reasonable computing capability. Although there are many hardware accelerators to implement the MUSIC algorithm [15][16][17], few reconfigurable processors are found. From what has been discussed above, the reconfigurable architecture is a balanced solution to implement the MUSIC algorithm.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Hardware Accelerator for the MUSIC Algorithm

Chen

Cheng

et al. 2019

Electronics

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As a classical DOA (direction of arrival) estimation algorithm, the multiple signal classification (MUSIC) algorithm can estimate the direction of signal incidence. A major bottleneck in the application of this algorithm is the large computation amount, so accelerating the algorithm to meet the requirements of high real-time and high precision is the focus. In this paper, we design an efficient and reconfigurable accelerator to implement the MUSIC algorithm. Initially, we propose a hardware-friendly MUSIC algorithm without the eigenstructure decomposition of the covariance matrix, which is time consuming and accounts for about 60% of the whole computation. Furthermore, to reduce the computation of the covariance matrix, this paper utilizes the conjugate symmetry property of it and the way of iterative storage, which can also lessen memory access time. Finally, we adopt the stepwise search method to realize the spectral peak search, which can meet the requirements of 1° and 0.1° precision. The accelerator can operate at a maximum frequency of 1 GHz with a 4,765,475.4 μm2 area, and the power dissipation is 238.27 mW after the gate-level synthesis under the TSMC 40-nm CMOS technology with the Synopsys Design Compiler. Our implementation can accelerate the algorithm to meet the high real-time and high precision requirements in applications. Assuming that the case is an eight-element uniform linear array, a single signal source, and 128 snapshots, the computation times of the algorithm in our architecture are 2.8 μs and 22.7 μs for covariance matrix estimation and spectral peak search, respectively.

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WITHDRAWN: Remote Music Teaching Classroom Based on FPGA High-Performance Algorithm

Lei

2020

Microprocessors and Microsystems

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Hardware acceleration of MUSIC based DoA estimator in MUBTS

Cited by 21 publications

References 5 publications

A Low Complexity, High Throughput DoA Estimation Chip Design for Adaptive Beamforming

A Low Complexity, High Throughput DoA Estimation Chip Design for Adaptive Beamforming

An Efficient Hardware Accelerator for the MUSIC Algorithm

WITHDRAWN: Remote Music Teaching Classroom Based on FPGA High-Performance Algorithm

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