Hardware acceleration of SVM-based traffic classification on FPGA

Groléat, Tristan; Arzel, Matthieu; Vaton, Sandrine

doi:10.1109/iwcmc.2012.6314245

Cited by 22 publications

(15 citation statements)

References 30 publications

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“…However, this increases the cycles needed to process a single vector. Hence, works that utilize such architectures have optimized it specifically for the vector dimensionality of the given problem and have been restricted to small scale data, with only a few hundred vectors and low dimensionality [9], [19], [20], and small-scale multiclass implementations [21] in order to be able to meet real-time constraints. In addition, these architectures cannot trade-off processing more SVs rather than vector elements, and hence, cannot efficiently deal with the different computational demands of the cascade SVM stages.…”

Section: Related Workmentioning

confidence: 99%

Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines

Kyrkou

Bouganis

Theocharides

et al. 2016

IEEE Trans. Neural Netw. Learning Syst.

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Section: Related Workmentioning

confidence: 99%

Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines

Kyrkou

Bouganis

Theocharides

et al. 2016

IEEE Trans. Neural Netw. Learning Syst.

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show abstract

“…When the vector dimensionality is high and the hardware resources are not available for a full parallel processing the architecture can be folded to process the elements in groups, however, this increases the cycles needed to process a single vector. Hence, works that utilize such architectures have optimized it specifically for the vector dimensionality of the given problem and have been restricted to small scale data, with only a few hundred vectors and low dimensionality(~100 elements) [10], [24], [25] and small-scale multiclass implementations [26] in order to be able to meet real-time constraints. In addition, these architectures cannot trade-off processing more SVs rather than vector elements, and hence, cannot efficiently deal with the different computational demands of the cascade SVM stages.…”

Section: Related Workmentioning

confidence: 99%

Boosting the Hardware-Efficiency of Cascade Support Vector Machines for Embedded Classification Applications

Kyrkou

Theocharides

Bouganis

et al. 2017

Int J Parallel Prog

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Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm capable of high accuracy rates for a different range of applications. When arranged in a cascade structure, SVMs can efficiently handle problems where the majority of data belongs to one of the two classes, such as image object classification, and hence can provide speedups over monolithic (single) SVM classifiers. However, the SVM classification process is still computationally demanding due to the number of support vectors. Consequently, in this paper we propose a hardware architecture optimized for cascaded SVM processing to boost performance and hardware efficiency, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings. The architecture was evaluated for the application of object detection on 800×600 resolution images on a Spartan 6 Industrial Video Processing FPGA platform achieving over 30 frames-per-second. Moreover, by utilizing the proposed hardware reduction method we were able to reduce the utilization of FPGA custom-logic resources by ~30%, and simultaneously observed ~20% peak power reduction compared to a baseline implementation.

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“…We used 6 flowlevel features in Table I; they demonstrate high classification accuracy with a reasonable hardware complexity [1], [7], [8]. Our classification engine classifies network traffic into 8 categories [18], including web, P2P download, direct download, streaming, game, mail, instant messaging, and distant control. We used a publicly available traffic trace provided by Tstat [19]; note the throughput performance of our classification engine does not depend on the traffic trace.…”

Section: Evaluation a Experimental Setupmentioning

confidence: 99%

Enabling High Throughput and Virtualization for Traffic Classification on FPGA

Prasanna

2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

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As an important network management task, Internet traffic classification requires high throughput. Virtualization is a technique sharing the same piece of hardware for multiple users. We present a high-throughput and virtualized architecture for online traffic classification. To explore massive parallelism, we provide a conversion from a decision-tree into a compact rule set table; we employ modular processing elements and map the table to a 2-dimensional pipelined architecture. To support hardware virtualization, we develop a novel dynamic update mechanism; it requires small resource overhead and has little impact on the overall throughput. To evaluate the performance of this architecture, we implement an online traffic classification engine on a state-of-the-art FPGA. Postplace-and-route results show that, our classification engine achieves 5-fold throughput compared with existing dynamically updatable online traffic classification engines on FPGA.

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Hardware acceleration of SVM-based traffic classification on FPGA

Cited by 22 publications

References 30 publications

Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines

Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines

Boosting the Hardware-Efficiency of Cascade Support Vector Machines for Embedded Classification Applications

Enabling High Throughput and Virtualization for Traffic Classification on FPGA

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