Hardware Acceleration of Video Edge Detection with Hight Level Synthesis on the Xilinx Zynq Platform

Abstract

The study conducted in the current paper consists of validating an original design flow for the rapid prototyping of real-time image and video processing applications on FPGAs. A video application for edge detection with Simulink HDL coder and Vivado High-Level Synthesis (HLS) has been designed as if the code was going to be executed on a conventional processor. The developed tools will automatically translate the code into VHDL hardware language using an advanced compilation technique. This amounts to embedding processors on Xilinx Zynq-7000 System on-Chip (SoC) device in an optimal manner. This automated hardware design flow reduces the time to create a prototype since only the high-level description is required. The design of the video edge detection system is implemented on Xilinx Zynq-7000 platform. The result of the implementation gave effective resource utilization and a good frame rate (95 FPS) under 170MHz frequency.

Efficient Real time Zynq 7000 FPGA deployment of optimized YOLOv2 deep leaning model for target detection, based on HDL Coder Methodology

“…By employing a double precision model based on MATLAB, this study determined the quantization error caused by choosing narrower "optimal" signal widths. This was accomplished utilizing the "FPGA in the loop" cosimulation function of MathWorks' HDL Verifier [20]. Less than 1% is the Root Mean Square (RMS) value of the quantization error.…”

“…These tools enable the execution of high-abstraction modelling methods, including transaction-level modelling, and enable verification teams to employ behavioural intellectual property throughout various initiatives [19]. Moreover, processors comprise an overpowering majority of contemporary semiconductor systems [20]. To incorporate custom circuitry, microprocessors, memory, and video processing devices (DSPs) into a single device, supplementary software or firmware must be implemented during the design phase.…”

“…Figure 1: Embedded System for FPGA image processingFor the proposed model-based design presented in figure2of executing the whole code on the FPGA inside the framework of a coherent subsystem, the user first defines the algorithms in a standalone Simulink model. When the platform-specific HDL code is ready, the HDL Coder tool employs the Xilinx Vivado development tools to silently synthesis it for the FPGA[20].…”

Model-Based FPGA Implementation of a 6-DoF Dynamical Model Accelerator

“…The MBD approach has been utilized in different studies to facilitate the development of a complex design. A softwaredefined radio in [21], a DC motor servo system model in [8], a video edge detection accelerator in [22] have been designed on FPGA using MBD approach. Instead of low-level design, Bolun et al have noted that ".…”