Hardware accelerator IP cores for real time Radar and camera-based ADAS

Abstract

The paper presents the design of HDL macrocells, working as hardware accelerators to achieve real time processing of some key functions of Advanced Driver Assistance Systems (ADAS). Particularly, the macrocells process in real time images from Radar and video-camera sensors implementing computing-intensive operations such as: pixel-level filtering, correction of distortions in large field-of-view cameras, multi-camera image fusion for panoramic view of car’s surround, traffic and road signs recognition, detection of obstacles for collision avoidance, and estimation of their distance and speed. The HDL macrocells are fully configurable and are synthesized in low-cost Artix-7 FPGA family, satisfying automotive-grade requirements. They can be integrated as accelerators in embedded hardware–software platforms to build a complete ADAS solution. To this aim, the macrocells have been synthesized also in a Zynq FPSoC. With respect to the state of the art, the proposed macrocells stand for their low-power and real time performanc

A Survey of Automotive Radar and Lidar Signal Processing and Architectures

“…Many aspects of radar signal processing can be accelerated in hardware [84]. One of the heaviest computational tasks is the CFAR algorithm, since this needs to perform many operations on big matrices.…”

“…Damnjanović et al [92] present a CHISEL model to generate 2D-FFT accelerators, both for basic range-Doppler processing and specialized for range-angle processing; they also present a custom memory controller to deal with radar data. Saponara [84] proposes a set of hardware macrocells to perform detection starting from the base-band signal. In particular, range, Doppler and azimuth processing is performed with a set of hardware FFT, while a hardware implementation of CA-CFAR is adopted to perform peak detection.…”