Hardware architectural support for control systems and sensor processing

Abstract

The field of modern control theory and the systems used to implement these controls have shown rapid development over the last 50 years. It was often the case that those developing control algorithms could assume the computing medium was solely dedicated to the task of controlling a plant, for example, the control algorithm being implemented in software on a dedicated Digital Signal Processor (DSP), or implemented in hardware using a simple dedicated Programmable Logic Device (PLD). As time progressed, the drive to place more system functionality in a single component (reducing power, cost, and increasing reliability) has made this assumption less often true. Thus, it has been pointed out by some experts in the field of control theory (e.g., Astrom) that those developing control algorithms must take into account the effects of running their algorithms on systems that will be shared with other tasks. One aspect of the work presented in this article is a hardware architecture that allows control developers to maintain this simplifying assumption. We focus specifically on the Proportional-Integral-Derivative (PID) controller. An on-chip coprocessor has been implemented that can scale to support servicing hundreds of plants, while maintaining microsecond-level response times, tight deterministic control loop timing, and allowing the main processor to service noncontrol tasks.In order to control a plant, the controller needs information about the plant's state. Typically this information is obtained from sensors with which the plant has been instrumented. There are a number of common computations that may be performed on this sensor data before being presented to the controller (e.g., averaging and thresholding). Thus in addition to supporting PID algorithms, we have developed a Sensor Processing Unit (SPU) that off-loads these common sensor processing tasks from the main processor.We have prototyped our ideas using Field Programmable Gate Array (FPGA) technology. Through our experimental results, we show our PID execution unit gives orders of magnitude improvement in response time when servicing many plants, as compared to a standard general software implementation. We also show that the SPU scales much better than a general software implementation. In addition, these execution units allow the simplifying assumption of dedicated computing medium to hold for control algorithm development.

Dynamic scheduling for networked control systems

“…The execution time of the scheduler is considered to be negligible, however control signal computation requires some time. Though the computation in Equation 2 looks simple, the practical implementation of such a controller requires some amount of sensor data processing [19] that contributes to the worst-case execution time of control signal computation. Let ci denote the worst case computation time for the control signal of the i'th control systemci is thus the worst-case execution time (WCET) of each job of the i'th control system.…”

Influence of PWM Torque Control Frequency in DC Motors by Means of an Optimum Design Method

“…Cristina et al [16] and Swapnil et al [17] implemented a fractional order PI and PID controllers on an FPGA-based device for DC motors. Vyas et al [18] and Renato et al [19] developed embedded controllers using a hardware/software co-design technique into an FPGA. A NIOS R II soft-processor was configured in a control system with self-tuning PID controller for an X-Y table by Ying et al [20].…”

Hardware/Software frameworks for control techniques to support real-time systems and runtime verification

“…needing a complete redesign of the hardware accelerator [15,49,74,50]). There have been efforts to overcome this limitation by modularizing hardware components to increase reusability [23,128]. However, these frameworks still heavily rely on the user having detailed hardware design expertise.…”