Hardware architecture for integrate-and-fire signal reconstruction on FPGA

Carvalho, Guilherme; Ferreira, Joao Canas; Tavares, Vítor Grade

doi:10.1109/dcis51330.2020.9268638

Cited by 2 publications

(4 citation statements)

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“…Our reconstruction method relies on the sampling kernel selection as well as introducing a new forward model to improve recovery from noisy hardware data. Compared to our previous results [16], here we present a simpler, straightforward proof for the recovery guarantees, which is based on using a partial sum of the measurements, resulting in more stable reconstruction. We demonstrate that in the presence of noise, the proposed reconstruction technique outperforms the method in [22].…”

Section: Introductionmentioning

confidence: 87%

“…The filtered output y(t) is sampled using an IF-TEM where the IF-TEM parameters are chosen to satisfy the inequality (16). In this particular case, the IF-TEM sampler resulted in 16 firing instants in one time period, as shown in Fig.…”

Section: B Numerical Evaluationmentioning

confidence: 99%

“…The parameters for the IF-TEM circuit were set to a value of κ = 3 • 10 −8 , with a bias of b = 3V and a threshold of δ = 1.5V . The specific time delays and amplitudes used in this input signal were chosen arbitrarily, and the IF-TEM parameters were selected to adhere to the constraints outlined in (16). As demonstrated in Fig.…”

Section: Hardware Experimentsmentioning

confidence: 99%

“…In this architecture, no global clock is required, making the IF-TEM sampler low energy. Furthermore, compared to its traditional amplitude-based ADCs, TEMs use extremely simple, entirely analog, low-power, and small size encoders [10], [14]- [16]. An IF-TEM integrates an input signal and then compares the integral to a threshold; if the threshold is met, the time instances are recorded [17]- [22].…”

Section: Introductionmentioning

confidence: 99%

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Hardware Prototype of a Time-Encoding Sub-Nyquist ADC

Naaman¹,

Glazer²,

Namer³

et al. 2023

Preprint

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Analog-to-digital converters (ADCs) are key components of digital signal processing. Classical samplers in this framework are controlled by a global clock. At high sampling rates, clocks are expensive and power-hungry, thus increasing the cost and energy consumption of ADCs. It is, therefore, desirable to sample using a clock-less ADC at the lowest possible rate. An integrate-and-fire time-encoding machine (IF-TEM) is a timebased power-efficient asynchronous design that is not synced to a global clock. Finite-rate-of-innovation (FRI) signals, ubiquitous in various applications, have fewer degrees of freedom than the signal's Nyquist rate, enabling sub-Nyquist sampling signal models. This work proposes a power-efficient IF-TEM ADC architecture and demonstrates sub-Nyquist sampling and FRI signal recovery. Using an IF-TEM, we implement in hardware the first sub-Nyquist time-based sampler. We offer a feasible approach for accurately estimating the FRI parameters from IF-TEM data. The suggested hardware and reconstruction approach retrieves FRI parameters with an error of up to -25dB while operating at rates approximately 10 times lower than the Nyquist rate, paving the way to low-power ADC architectures.Index Terms-Brain-inspired computing, analog-to-digital conversion (ADC), time-based sampling hardware, integrate and fire TEM (IF-TEM), sub-Nyquist sampling, finite-rate-of innovation (FRI) signals.

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Section: Introductionmentioning

confidence: 87%

Section: B Numerical Evaluationmentioning

confidence: 99%

Section: Hardware Experimentsmentioning

confidence: 99%