Hardware architecture of bi-cubic convolution interpolation for real-time image scaling

Abstract

This paper presents two hardware architectures of bi-cubic convolution interpolation termed Parallelized Row Column Interpolation Architecture (PRCIA) and Serialized Row Column Interpolation Architecture (SRCIA) for real-time image scaling . These architectures factor in the challenges of high computational complexity, redundant computations and repeated memory accesses, which were otherwise not explicitly addressed in existing architectures. Besides, the proposed architectures also employ parallel computations to improve the throughput for realtime applications. The proposed architectures have been emulated and tested on Virtex-6 FPGA. The emulated PRCIA and SRCIA are able to scale input grayscale images of dimensions up to 640 × 480 at 59 and 48 frames per second respectively with arbitrary scaling factors up to 4 in both dimensions.

Low-Cost Implementation of Bilinear and Bicubic Image Interpolation for Real-Time Image Super-Resolution

“…However, by this choice, the hardware resources are reduced. Notably, even if we utilize large size images, the hardware resources are much less than the other works like [11,14,22,24].…”

“…The architecture presented in [11,19] stores all of the image pixels in external memory. However, in our proposed architecture, by using the sliding window, which is presented in detail in Fig.…”

“…The bicubic interpolation algorithm addressed in this paper is a simplified computation complexity version of the algorithm presented in [11]. The proposed architecture is real-time and applicable in many security and surveillance applications, such as identifying the car plates, authentications, remote sensing [12], and similar practices, where real-time processing is necessary.…”

“…In [18], a Real-time FPGA Implementation of Barrel distortion correction method by using bilinear interpolation is presented. The architecture in [11] grants high output quality but demands very high output resources; hence consumes high power.…”

“…In [11,19], the bicubic interpolation is implemented. These architectures store the entire image pixels in external memory.…”