Hardware Architecture of MAP Algorithm for Turbo Codes Implemented in a FPGA

Marín, Roberto Ramírez; Garcia, A.; Perez, L.F.G.; Villarruel, J.E.G.

doi:10.1109/coniel.2005.44

Cited by 4 publications

References 4 publications

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Memory Efficient, High Speed Implementation of MAX LOG MAP Decoder for CCSDS Turbo codes

Varghese

Ansha²,

Sreelal

et al. 2013

2013 Third International Conference on Advances in Computing and Communications

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This paper presents an efficient and reduced memory design and FPGA implementation of Max-Log-maximum a posteriori (MAP) turbo decoder for CCSDS telemetry channel coding standard. Efficient implementation comes from using integer arithmetic, sliding window(SW) technique and compact hardware and memory management. The memory requirements are systematically investigated and optimized for the soft inputs and metrics used. A shift register based sliding window technique along with a single cycle interleaver address generator made it possible to process a trellis stage per clock cycle. Simulations are done in MATLAB to assess the BER performance of the design in an AWGN channel. This paper tells that, about 81% of memory reduction has been achieved using proposed sliding window technique with 1.03cycles/stage decoding speed. By introducing a combinational logic for interleaver address generation, 99% of memory has been reduced for that purpose. Using 4 bit soft inputs and by weighing the apriori values shows only a 0.6dB degradation in the BER performance from log map floating point implementation. By careful manipulation of the hardware, we implement the whole turbo decoder with a single decoder structure which has a core usage of 76% and ,SRAM utilization of 22% of the selected FPGA to achieve a throughput of more than 31 MBps per full iteration at an operating frequency of 64 MHz. Index Terms-Turbo decoder, Max-Log-MAP, FPGA I.

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