Hardware architectures for the H.265/HEVC discrete cosine transform

Abstract

This study presents a design methodology for the two-dimensional (2D) discrete cosine transform dedicated for H.265/ HEVC hardware encoders. The methodology decomposes matrix multiplications for different transform sizes into some steps based on the division of transform units into fixed-size blocks. The modified order of processed blocks allows a significant reduction of the size of the transposition buffer. As a consequence, the resource consumption of the whole 2D-transform architecture is decreased. Separate transform cores assigned to two transform stages increase the throughput more than twice. The decomposition enables different hardware configurations of the architectures. Particularly, the architectures applying the proposed methodology are parametrically specified in VHDL, and configuration parameters enable the tradeoff between resources and the throughput. Furthermore, the interface adaptation to desired horizontal and vertical sizes is possible. The use of regular multipliers allows the support for transforms specified in other video standards. Computational elements embedded in architectures are well-suited to FPGA devices, which improves the area-speed efficiency. Synthesis results show that they can operate at 200 and 400 MHz when implemented in FPGA Arria II and TSMC 90 nm, respectively.

Efficient architecture of variable size HEVC 2D-DCT for FPGA platforms

“…The results in Table II and III indicate that our proposed idea is generic and it is not limited to any specific FPGA company. Both the reference [24] and this work support variable DCT sizes. Using the same FPGA platform, our proposed architecture saves LUT resources by 32% and DSP blocks by 75%.…”

“…DCT transforms images from spatial-domain into frequency-domain, and provides a more efficient representation of information. A 1D-DCT computation of an N×N block size can be expressed as [10,24] …”

“…Therefore, the study of HEVC FPGA implementation is gaining more and more attention. In order to satisfy real-time and high-efficiency coding in these emerging video applications, a few design methodologies and circuit architectures have been developed [11,[18][19][20][21][22][23][24]. In [11], the authors presented an IDCT implementation with zero-column skipping technique to boost energy and area efficiency.…”

“…In [22], a new algorithm and processing architecture for 2D-DCT were presented to achieve higher energy efficiency. Recently, the researchers in [23][24] proposed FPGA-based 2D-DCT with improved area-speed efficiency. [23][24] are initial trials to efficiently utilize features and dedicated components of FPGA platforms.…”

“…Recently, the researchers in [23][24] proposed FPGA-based 2D-DCT with improved area-speed efficiency. [23][24] are initial trials to efficiently utilize features and dedicated components of FPGA platforms. However, the design strategy of allocating FPGA resources to fit DCT architectures are not elaborated in details.…”