Hardware-Based I/O Virtualization for Mixed Criticality Real-Time Systems Using PCIe SR-IOV

Muench, Daniel; Isfort, Ole; Mueller, Kevin; Paulitsch, Michael; Herkersdorf, Andreas

doi:10.1109/cse.2013.109

Cited by 19 publications

(22 citation statements)

References 4 publications

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“…An example for such an adaptable part is an I/O module on a shared I/O card (cf. figure 1, figure 13 and [2]). The host-side part of the shared I/O card -the PCIe part -is reused.…”

Section: A Concept Iterative Fpga Implementation and Iterative Certimentioning

confidence: 88%

“…Fig. 13 and [2]) which schedules requests for the virtual interfaces on the host side. Such a module is also self-contained and operates with a defined interface.…”

Section: B) Resource Utilization and Optimizationmentioning

confidence: 99%

“…A further application of an adaptable part is an arbitration module of a shared I/O card (cf. figure 1, figure 13 and [2]) which schedules requests for the virtual interfaces on the host side. Another example is a buffer module with configurable buffer sizes for an I/O module of an I/O card.…”

Section: A Concept Iterative Fpga Implementation and Iterative Certimentioning

confidence: 99%

“…Since I/O interfaces are shared resources on an integrated platform, the correct use of the shared resources needs to be demonstrated for certification. For example, providing spatial separation [1] and temporal separation [2] in I/O subsystems is an important item.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, this paper presents a design approach to reduce complexity and ease safety certification. This type of sharing is also called hardware-based I/O virtualization [1] [2] (cf. Fig.…”

Section: Introductionmentioning

confidence: 99%

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Iterative FPGA Implementation Easing Safety Certification for Mixed-Criticality Embedded Real-Time Systems

Muench

Paulitsch

Honold

et al. 2014

2014 17th Euromicro Conference on Digital System Design

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The design and operation of an aircraft, a railway, and a nuclear power station that include either safety-critical or safety-related systems require a proof that its safety is assured. The process providing this proof is called certification. This paper suggests an iterative FPGA implementation and iterative certification concept for FPGA-based systems to provide design-time adaptability while the complexity is still kept low to ease certification.The practical evaluation of this concept demonstrates that reuse at implementation level of a previously implemented part is to 100% usable for iterative certification. Regarding the resource utilization and complexity, the evaluation shows that there are potential savings in resource utilization and complexity compared to conventional run-time configurable designs. Iterative certification reduces the recertification of a whole design to a recertification of the changed part only and a verification tool qualification. It is shown that tool qualification can be accomplished with relatively moderate effort. Therefore, the presented concept substantially eases the certification process when using modular design and building block reuse.

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“…An example for such an adaptable part is an I/O module on a shared I/O card (cf. figure 1, figure 13 and [2]). The host-side part of the shared I/O card -the PCIe part -is reused.…”

Section: A Concept Iterative Fpga Implementation and Iterative Certimentioning

confidence: 88%

“…Fig. 13 and [2]) which schedules requests for the virtual interfaces on the host side. Such a module is also self-contained and operates with a defined interface.…”

Section: B) Resource Utilization and Optimizationmentioning

confidence: 99%

Section: A Concept Iterative Fpga Implementation and Iterative Certimentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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