Reconfigurable hardware is a promising technology for implementing firewalls, routing mechanisms, and new protocols for evolving high-performance network systems. This work presents a novel deterministic approach for a Range Enhanced Reconfigurable Packet Classification Engine (RERPEC) based on the number of rules on FPGAs. The proposed framework uses a RAM established
Ternary Match
to represent the prefix and the range prefix and efficient rule-reordering for priority selection to get both best-match and multi-match in the same architecture. The recommended framework exhibits
3.2 Mbits
of LUT-RAM based TCAM to hold a maximum of
31.3 K
of 104 −
bit
rules
with
520 MPPS
. LUT-RAM, along with BRAM, shows
4 Mbits
of TCAM space to implement
38.5 K
of 104 −
bits
rules
to sustain a throughput of
400 MPPS
on Virtex-7 FPGA. The complete architecture offers scalability, better resource utilization (minimum of
50%
), representation of inverse prefix with single entry, range expansion with a single rule, getting best and multi-match, and determination of the required number of FPGA resources for a particular dataset.