Hardware Based Scale- and Rotation-Invariant Feature Extraction: A Retrospective Analysis and Future Directions

Automatic Number Plate Recognition on FPGA i AbstractIntelligent Transportation Systems (ITSs) play an important role in modern traffic management, which can be divided into intelligent infrastructure systems and intelligent vehicle systems. Automatic Number Plate Recognition systems (ANPRs) are one of infrastructure systems that allow users to track, identify and monitor moving vehicles by automatically extracting their number plates. ANPR is a well proven technology that is widely used throughout the world by both public and commercial organisations. There are a wide variety of commercial uses for the technology that include automatic congestion charge systems, access control and tracing of stolen cars. The fundamental requirements of an ANPR system are image capture using an ANPR camera and processing of the captured image. The image processing part, which is a computationally intensive task, includes three stages: Number Plate Localisation (NPL), Character Segmentation (CS) and Optical Character Recognition (OCR). The common hardware choice for its implementation is often high performance workstations. However, the cost, compactness and power issues that come with these solutions motivate the search for other platforms. Recent improvements in low-power high-performance Field Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs) for image processing have motivated researchers to consider them as a low cost solution for accelerating such computationally intensive tasks.Current ANPR systems generally use a separate camera and a stand-alone computer for processing. By optimising the ANPR algorithms to take specific advantages of technical features and innovations available within new FPGAs, such as low power consumption, development time, and vast on-chip resources, it will be possible to replace the high performance roadside computers with small in-camera dedicated platforms. In spite of this, costs associated with the computational resources required for complex algorithms together with limited memory have hindered the development of embedded vision platforms.The work described in this thesis is concerned with the development of a range of image The overall results achieved show that the entire ANPR system can be implemented on a single FPGA that can be placed within an ANPR camera housing to create a stand-alone unit. As the benefits of this are drastically improve energy efficiency and removing the need for the installation and cabling costs associated with bulky PCs situated in expensive, cooled, waterproof roadside cabinets. Certificate of OriginalityAutomatic Number Plate Recognition on FPGA iii Certificate of OriginalityI hereby certify that the work presented in this report is my original research and has not been presented for a higher degree at any other university or institute.

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“…Therefore, GPUs are unsuitable for embedded vision applications with restricted power constraints [20].…”

Section: Digital Signal Processorsmentioning

confidence: 99%

Automatic Number Plate Recognition on FPGA

Zhai

Bensaali

McDonald-Maier

2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

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“…GPU plus CPU obtain impressive processing speed, but they still require a PC system and more power supply. Special purpose hardwares on FPGA can provide a good balance between speed and energy, these works are reported in Ehsan's survey [6]. Ko [7] implemented SIFT on a BlackFin DSP inside a wireless camera network.…”

Section: Introductionmentioning

confidence: 99%

DSP-Based Parallel Implementation of Speeded-Up Robust Features

Liao

Wang

Miao

et al. 2011

IEICE Trans. Inf. & Syst.

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SUMMARYRobust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.

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Hardware Based Scale- and Rotation-Invariant Feature Extraction: A Retrospective Analysis and Future Directions

Cited by 2 publications

References 25 publications

Automatic Number Plate Recognition on FPGA

Automatic Number Plate Recognition on FPGA

DSP-Based Parallel Implementation of Speeded-Up Robust Features

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