Hardware-based systems for partial sorting of streaming data

Rjabov, Artjom

doi:10.1109/bec.2016.7743728

Cited by 9 publications

(1 citation statement)

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“…The highlight from table is delay, which is minimal and ignorable. https://www.indjst.org/ (16) Comparison-free sorter unit (16) Table 4 provides comparison of FPGA resource utilization of proposed approach against various recent sorting methods (15,18,22,23) . In this table, proposed architecture consumes less resource for number of elements N=128 and each input size of 32-bits in width.…”

Section: Resultsmentioning

confidence: 99%

FPGA Design for Low Delay Comparison-free, Odd-even Merge Sorter

Preethi¹,

Mohan²,

Augustine³

et al. 2022

IJST

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Background/Objective: Reduced Instruction Set Computer (RISC) is one of the most common types of architecture involved in microprocessor that has several blocks. There is a lot of scope that can be observed in optimizing these blocks involved in RISC resulting in better and effective microprocessors. Method: One of the sub-blocks that plays a prominent role in RISC architecture is sorter, and it can be achieved by modifying the sorting algorithm. Findings: A novel odd-even comparison-free sorting that assists in arranging N several data components in roughly N clock cycles is proposed here. N identical blocks are arranged in streamlined manner that are stacked using handful primary logic elements resulting in sorter computation. In the proposed framework, classification and categorization activities are executed in a channeled fashion. The entire design is amalgamated for numerous data sets from imitated indiscriminately generated data elements to all exceptional elements, to all the similar elements, and also from random to completely sorted data elements. It has been observed that, the algorithm appears impartial to the input ordering. Novelty: comparison-free unit was implemented on odd-even sorter. Synthesis results indicate that the proposed approach consumes reasonably low FPGA resource. The number of elements consider for sorting was N=8, this architecture takes per element sorting delay as approximately 2.1 to 4.4 ns (1 clock cycle).

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Section: Resultsmentioning

confidence: 99%