Hardware design and implementation of disparity image post-processing for noise reduction by standard deviation

Abstract

This paper proposes a disparity post-processing method for noise reduction using standard deviation, and presents the design and implementation of pipelined dedicated hardware architecture for the real-time processing performance. In the proposed method, the optimal standard deviation is calculated first using the parameters generated by iterative experiments. Through these parameters, we can determine whether the pixel of interest has the correct disparity value and can remove error pixels. We implemented the proposed dedicated hardware architecture on a Xilinx Virtex5 FPGA. The average operating frequency of this system operated up to 80M Hz, which enabled real-time streaming video processing at 60fps.