Hardware Design of Approximate Matrix Multiplier based on FPGA in Verilog

Gupta, Ankit; Suneja, Kriti

doi:10.1109/iciccs48265.2020.9121004

Cited by 5 publications

(4 citation statements)

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“…Using blocking technology to improve bandwidth and storage efficiency, the ResNet-18 CNN model was implemented on XC7VX690T FPGA. Running at a clock frequency of 200MHz, the average throughput was 383 GOPS, which was a significant improvement in comparison to the work of Asgar Abbaszadeh et al In the same year, Ankit Gupta et al [81] made a tradeoff between accuracy and performance and proposed a new approximate matrix multiplier structure, which greatly improved the speed of matrix multiplication by introducing a negligible error amount and an approximate multiplication operation.…”

Section: ) Winograd Fast Convolution Algorithmmentioning

confidence: 96%

“…As shown in Figure 6, according to different design concepts and requirements, FPGA-based neural network optimization technology can be roughly divided into optimization for data and operation, optimization for bandwidth, and optimization for memory and access, among others, which are introduced in detail below. [71][72][73][74][75][76][77][78], less computations [79][80][81], improve calculation speed [82][83][84][85], Winograd fast convolution algorithm [86][87][88][89][90][91], Im2col convolution optimization algorithm [92][93][94][95][96][97], pipelined design [98][99][100][101][102], Roofline model [103][104][105], ping-pong cache [106][107][108][109], input feature map reuse [110,111], filter reuse [111,112], convolutional reuse [110]…”

Section: Neural Network Optimization Technology Based On Fpgamentioning

confidence: 99%

“…Neural network optimization technology based on FPGA. (fixed-point quantization[71][72][73][74][75][76][77][78], less computations[79][80][81], improve calculation speed[82][83][84][85], Winograd fast convolution algorithm[86][87][88][89][90][91], Im2col convolution optimization algorithm[92][93][94][95][96][97], pipelined design[98][99][100][101][102], Roof-line model[103][104][105], ping-pong cache[106][107][108][109], input feature map reuse[110,111], filter reuse[111,112], convolutional reuse[110][111][112], time reuse or space reuse[111], standardize data access and storage…”

mentioning

confidence: 99%

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A Review of the Optimal Design of Neural Networks Based on FPGA

Wang

Luo

2022

Applied Sciences

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Deep learning based on neural networks has been widely used in image recognition, speech recognition, natural language processing, automatic driving, and other fields and has made breakthrough progress. FPGA stands out in the field of accelerated deep learning with its advantages such as flexible architecture and logic units, high energy efficiency ratio, strong compatibility, and low delay. In order to track the latest research results of neural network optimization technology based on FPGA in time and to keep abreast of current research hotspots and application fields, the related technologies and research contents are reviewed. This paper introduces the development history and application fields of some representative neural networks and points out the importance of studying deep learning technology, as well as the reasons and advantages of using FPGA to accelerate deep learning. Several common neural network models are introduced. Moreover, this paper reviews the current mainstream FPGA-based neural network acceleration technology, method, accelerator, and acceleration framework design and the latest research status, pointing out the current FPGA-based neural network application facing difficulties and the corresponding solutions, as well as prospecting the future research directions. We hope that this work can provide insightful research ideas for the researchers engaged in the field of neural network acceleration based on FPGA.

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Section: ) Winograd Fast Convolution Algorithmmentioning

confidence: 96%

Section: Neural Network Optimization Technology Based On Fpgamentioning

confidence: 99%

mentioning

confidence: 99%

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A Review of the Optimal Design of Neural Networks Based on FPGA

Wang

Luo

2022

Applied Sciences

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“…hence, an aggressor can't figure out the design on account of the confusion, and the chip can't be overproduced with out ability of the key. moreover, design degree strategies comprehensive of cell disguise [8] will be utilized as equipment muddling and faker contacts are utilized to protect contrary to aggressors. The organization of in vogue cells with various functionalities is made to seem indistinguishable in the cover approach.…”

Section: Introductionmentioning

confidence: 99%

Cube Stripping Function and Logic Restoration Based Hardware Security

P¹,

Rangarajan²,

Selvi³

2022

ESP-JETA

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Guaranteeing security without compromising the exhibition and adaptability of a gadget is basically an exceptionally difficult endeavor for Researchers and Practitioners Approximate circuits (AxCs) tradeoff computational exactness against upgrades in equipment place, put off, or power consumption. IP center transporters who need to make such circuits need to persuade clients regarding the subsequent guess superior grade. As an answer, underwrite PUF based absolutely confirmation conveying AxCs. the vender makes a surmised IP center by and large with an authentication that demonstrates the estimation fine. The proof endorsement is packaged with the surmised IP center and shipped off to the client. We utilize the PUF reaction to free the element of the chip. The benefactor can authoritatively confirm the guess good of the IP center at a section of the standard computational expense for formal confirmation.

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