Hardware-Efficient Logic Camouflaging for Monolithic 3-D ICs

Chen, Yan; Dofe, Jaya; Yu, Qiaoyan; Salman, Emre

doi:10.1109/tcsii.2017.2749523

Cited by 19 publications

(16 citation statements)

References 14 publications

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“…6.4. Regarding prior art on 3D LC [22], [23], recall that they require a trusted FEOL facility; hence, their schemes are not directly comparable to ours. Also, at the time of writing, their libraries and protected designs were not available to us for a detailed study.…”

Section: Case Study On Cep and Jpegmentioning

confidence: 83%

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A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Patnaik

Ashraf²,

Sinanoglu³

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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Split manufacturing (SM) and layout camouflaging (LC) are two promising techniques to obscure integrated circuits (ICs) from malicious entities during and after manufacturing. While both techniques enable protecting the intellectual property (IP) of ICs, SM can further mitigate the insertion of hardware Trojans (HTs). In this paper, we strive for the "best of both worlds," that is we seek to combine the individual strengths of SM and LC. By jointly extending SM and LC techniques toward 3D integration, an up-and-coming paradigm based on stacking and interconnecting of multiple chips, we establish a modern approach to hardware security. Toward that end, we develop a security-driven CAD and manufacturing flow for 3D ICs in two variations, one for IP protection and one for HT prevention. Essential concepts of that flow are (i) "3D splitting" of the netlist to protect, (ii) obfuscation of the vertical interconnects (i.e., the wiring between stacked chips), and (iii) for HT prevention, a security-driven synthesis stage. We conduct comprehensive experiments on DRC-clean layouts of multi-million-gate DARPA and OpenCores designs (and others). Strengthened by extensive security analysis for both IP protection and HT prevention, we argue that entering the third dimension is eminent for effective and efficient hardware security.

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Section: Case Study On Cep and Jpegmentioning

confidence: 83%

“…6 for more comparative results. As for 3D integration, Yan et al [23] proposed LC for monolithic 3D ICs, and Gu et al [22] apply LC for 3D ICs, albeit using regular 2D LC schemes. Hence, while promising, both works still require trusted FEOL facilities.…”

Section: Layout Camouflagingmentioning

confidence: 99%

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Patnaik

Ashraf²,

Sinanoglu³

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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“…For example, the NAND-NOR-XOR primitive of [50] would incur 5.5× power, 1.6× delay, and 4× area cost compared to a regular NAND gate. 4 In contrast, the work in [184] report on average only 25% power cost, 15% delay cost, and 43% area savings compared to regular 2D gates.…”

Section: Confidentiality and Integrity Of Hardwarementioning

confidence: 99%

“…This idea serves for labelling and authentication of chips (or other goods, for that matter). Loosely related, because without [182] 2.5D IP protection; SM Interposer [82] 2.5D Trojan prevention; SM Interposer [183] F2F IP protection; SM, camouflaging Parts of 3D IC [184] M3D IP protection; camouflaging Whole 3D IC [185] F2F IP protection, Trojan prevention; Only BEOL SM, camouflaging [186] TSV Probing protection; enclosure Whole 3D IC [187,188] TSV Side-channel mitigation; enclosure Whole 3D IC [4] 2.5D Runtime monitoring; separation Interposer the need for nanowires, the authors in [93] proposed the concept of plasmonics-enhanced optical PUFs and provide physical-simulation results and a security analysis.…”

Section: Nanowires and Nwfetsmentioning

confidence: 99%

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Hardware Security For and Beyond CMOS Technology

Knechtel¹

2020

Proceedings of the 2020 International Symposium on Physical Design

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As with most aspects of electronic systems and integrated circuits, hardware security has traditionally evolved around the dominant CMOS technology. However, with the rise of various emerging technologies, whose main purpose is to overcome the fundamental limitations for scaling and power consumption of CMOS technology, unique opportunities arise also to advance the notion of hardware security. In this paper, I first provide an overview on hardware security in general. Next, I review selected emerging technologies, namely (i) spintronics, (ii) memristors, (iii) carbon nanotubes and related transistors, (iv) nanowires and related transistors, and (v) 3D and 2.5D integration. I then discuss their application to advance hardware security and also outline related challenges. CCS CONCEPTS• Security and privacy → Security in hardware; • Hardware → Emerging technologies.

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Hardware and Information Security Primitives Based on 2D Materials and Devices

Wali

Das

2023

Advanced Materials

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Hardware security is a major concern for the entire semiconductor ecosystem that accounts for billions of dollars in annual losses. Similarly, information security is a critical need for the rapidly proliferating edge devices that continuously collect and communicate a massive volume of data. While silicon‐based complementary metal‐oxide‐semiconductor technology offers security solutions, these are largely inadequate, inefficient, and often inconclusive, as well as resource intensive in time, energy, and cost, leading to tremendous room for innovation in this field. Furthermore, silicon‐based security primitives have shown vulnerability to machine learning (ML) attacks. In recent years, 2D materials such as graphene and transition metal dichalcogenides have been intensely explored to mitigate these security challenges. In this review, 2D‐materials‐based hardware security solutions such as camouflaging, true random number generation, watermarking, anticounterfeiting, physically unclonable functions, and logic locking of integrated circuits (ICs) are summarized with accompanying discussion on their reliability and resilience to ML attacks. In addition, the role of native defects in 2D materials in developing high entropy hardware security primitives is also examined. Finally, the existing challenges for 2D materials, which must be overcome for large‐scale deployment of 2D ICs to meet the security needs of the semiconductor industry, are discussed.

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Hardware-Efficient Logic Camouflaging for Monolithic 3-D ICs

Cited by 19 publications

References 14 publications

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Hardware Security For and Beyond CMOS Technology

Hardware and Information Security Primitives Based on 2D Materials and Devices

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