Hardware efficient multiplier‐less multi‐level 2D DWT architecture without off‐chip RAM

Abstract

This study presents a multi-level 2D discrete wavelet transform (DWT) architecture without off chip RAM. Existing architectures use one off-chip RAM to store the image data, which increases the complexity of the system. For one-chip design, line-based architecture based on modified lifting scheme is proposed. By replacing the multipliers with canonic sign digit multipliers, a critical path of one full-adder delay is achieved. As per theoretical estimate, for three-level 2DDWT with an image of N × N size, the proposed architecture requires 123 adders, 66 subtracters, 167 registers, temporal memory of 7.5N words and input RAM of 3N bytes. The estimated

Power and Area Efficient Radix-8 Booth Multiplier for 2-D DWT Architecture

“…The ADP of the CSD architecture is 29.018% excess ADP (EADP) and for booth multiplier it is 28.22% EADP than proposed Booth multiplier and the PDP of the CSD architecture is 26.12% excess PDP (EPDP) and in booth multiplier it is 34.97% EPDP than proposed architecture are computed and it shows how much better performances does the proposed method gives than the existed method relating to area and power. The delay is not improved in proposed architecture than [11] because the critical path is considered from the truncated part. The throughput for the 2D DWT architecture in CSD based implementation has extra four cycles than the proposed architecture.…”

“…C. Wu, W. Zhang and J. Liu [11] proposed a 2D DWT architecture with multi-level without off-chip RAM using the CSD representation for the multiplier coefficients. The CSD makes use of shift and add operation for the implementation of the multiplier.…”

“…Normally in the existing architecture [11] the 1D DWT architecture consumes 12 clock cycles and the proposed architecture consumes 8 clock cycles for the operation by removing the extra 4 registers. By reducing the number of registers speed is increased and thus enhances the performance.…”

An Internal Folded Hardware-Efficient Architecture for Lifting-Based Multi-Level 2-D 9/7 DWT

“…Thus, they can be considered as basic operations and can be reused to reduce the computing resources. For further analysis of the pipeline structure shown in Figure 1, considering that Tm ≈ 2Ta [14], the multiplication and addition operations in each basic operation can be performed simultaneously without any bad effect on the critical path, the multiplication items of the flipping method (2)-(4) arrive at least one clock cycle ahead of their respective addition items. For instance, if the multiplication item x(2n) in (2) arrives at the Xth clock cycle, the addition items y(2n + 1) and y(2n − 1) will be obtained through (1) at the Xth + 1 clock cycle at least, where X is defined as the number of clock cycles.…”

“…Besides, [13] discussed different data scanning methods and optimized the scanning sequence to decrease the area of the frame memory for the unfolded structure. Recently, Wu [14] introduced the CSD multiplier to decline the critical path to Ta. Nonetheless, multi-clock control system is necessary.…”