Hardware Implementation of 24-bit Vedic Multiplier in 32-bit Floating-Point Divider

Hanuman, C. R. S.; Kamala, J.

doi:10.1109/iceese.2018.8703551

Cited by 6 publications

(4 citation statements)

References 9 publications

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“…A conventional 3-bit VM comprises nine AND gates, three half adders (HA)s, and three full adders (FA)s as depicted in Figure 2 [25]. The multiplier has two (3-bit) inputs…”

Section: A 3-bit Vedic Based Squaring Operationmentioning

confidence: 99%

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Vedic-Based Squarers with High Performance

Al-Assfor

AL-Furati

Rashed

2021

IJEEI

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Squaring operation represents a vital operation in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, a novel design for a 6-bit squarer basing on the Vedic multiplier (VM) is offered in this work. The squarer design utilizes dedicated 3-bit squarer modules, a (3*3) VM, and an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with the amended design of XOR gate to perform fast partial-products addition. The 6-bit squarer circuit can readily be expanded for larger sizes such as 12-bit and 24-bit numbers which are useful for squaring the mantissa part of 32-bit floating-point numbers. The paper also offers three architectures for 24-bit squarer using pipelining concept used in various stages. All these squaring circuits are designed in VHDL and implemented by Xilinx ISE13.2 and FPGA. The synthesis results reveal that the offered 6-bit, 12-bit, and 24-bit squarer circuits introduce eminent outcomes in terms of delay and area when utilizing IBK-CSLA with amended XOR gate. Also, it is found that the three architectures of 24-bit squarer present dissimilar delay and area, and the architecture design based on 3-bit squarer modules with (3*3) VM introduces the lowest area and delay.

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“…A conventional 3-bit VM comprises nine AND gates, three half adders (HA)s, and three full adders (FA)s as depicted in Figure 2 [25]. The multiplier has two (3-bit) inputs…”

Section: A 3-bit Vedic Based Squaring Operationmentioning

confidence: 99%

“…The output P4 is replaced with NOT, OR, and AND gates, and the final squaring bit P5 is minimized to AND gate only. The calculation steps of the proposed 6-bit squarer for an input data X= (X5 X4 X3 X2 X1 X0) can be derived based on the conceptions of (3*3) VM discussed in [25], as follows…”

Section: Dedicated 3-bit Squarermentioning

confidence: 99%

Vedic-Based Squarers with High Performance

Al-Assfor

AL-Furati

Rashed

2021

IJEEI

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show abstract

“…The primary method used to layout the typical multiplication algorithm such as Array Techniques, Booth's Technique, Shift & Add Techniques and many more techniques. The existing method shows a novel methodology in wherein multiplier segment is executing by use of antiquated Vedic Mathematics [9]. Vedic Multiplier is one of the traditional and ancient one that focus on being fast and low power.…”

Section: Introductionmentioning

confidence: 99%

A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

Gavaskar

Malathi

Ravivarma

et al. 2021

Preprint

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The Multiply Accumulate (MAC) unit constructed using antiquated Vedic mathematical practice and the efficiency of the vertical and transversely of Vedic approach for multiplication, which gives a distinction in genuine cycle of Multiplier itself. Vedic-Mathematics is depend on 16-Sutras, in that Urdhva-Triyakbhyam (UT) more productive one. It literally means vertical and cross wise operations. It eliminates unwanted multiplication and allows the parallel creation of partial products and addition steps. The adders are utilized to append the partial-product generated in the Vedic mathematics methodology to drops the combinational lag. MAC is an essential unit in the digital signal processors, to show the characters like speed, power as well as area. Hence, finer multiplier plans are to increase the order of the system. The Modified sum product algorithm based Vedic multiplier is one such promising solution. It has a rapid multiplication process and reaches a less calculation complexity above its traditional multiplier. Array multiplier, Baugh-Wooley multiplier, Wallace-tree multiplier and Vedic multiplier were created in the existing work. In proposed work Vedic multiplier, using modified sum product algorithm was designed. The structure design coded in verilog and parameter analysis was done in Xilinx. The parameters like delay as well as power were compare between existing and proposed. When comparing with different multiplier with our proposed work delay get reduced. Comparing with existing multiplier the proposed 4x4 Vedic multiplier have 49.12% reduction in delay. Comparing with existing multiplier the proposed Vedic 4x4 multiplier have 42.51% reduction in power.

show abstract

Section: Introductionmentioning

confidence: 99%

A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

Gavaskar¹,

Malathi²,

Ravivarma³

et al. 2021

Wireless Pers Commun

View full text Add to dashboard Cite

The Multiply Accumulate (MAC) unit constructed using antiquated Vedic mathematical practice and the e ciency of the vertical and transversely of Vedic approach for multiplication, which gives a distinction in genuine cycle of Multiplier itself. Vedic-Mathematics is depend on 16-Sutras, in that Urdhva-Triyakbhyam (UT) more productive one. It literally means vertical and cross wise operations. It eliminates unwanted multiplication and allows the parallel creation of partial products and addition steps. The adders are utilized to append the partial-product generated in the Vedic mathematics methodology to drops the combinational lag. MAC is an essential unit in the digital signal processors, to show the characters like speed, power as well as area. Hence, ner multiplier plans are to increase the order of the system. The Modi ed sum product algorithm based Vedic multiplier is one such promising solution. It has a rapid multiplication process and reaches a less calculation complexity above its traditional multiplier. Array multiplier, Baugh-Wooley multiplier, Wallace-tree multiplier and Vedic multiplier were created in the existing work. In proposed work Vedic multiplier, using modi ed sum product algorithm was designed. The structure design coded in verilog and parameter analysis was done in Xilinx. The parameters like delay as well as power were compare between existing and proposed. When comparing with different multiplier with our proposed work delay get reduced. Comparing with existing multiplier the proposed 4x4 Vedic multiplier have 49.12% reduction in delay. Comparing with existing multiplier the proposed Vedic 4x4 multiplier have 42.51% reduction in power.

show abstract

Hardware Implementation of 24-bit Vedic Multiplier in 32-bit Floating-Point Divider

Cited by 6 publications

References 9 publications

Vedic-Based Squarers with High Performance

Vedic-Based Squarers with High Performance

A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

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