Hardware implementation of a disparity estimation scheme for real-time compression in 3D imaging applications

Chaikalis, D.; Sgouros, N.; Maroulis, Dimitris; Papageorgas, Panagiotis

doi:10.1016/j.jvcir.2007.09.003

Cited by 11 publications

(12 citation statements)

References 17 publications

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“…The applied compression scheme is P-I for 1 N = , P-I-P for 2 N = and P-P-I-P-P for 3 N = . Memory read operations are minimized since the EI pixel values are only transferred once for the calculations [9]. According to the unidirectional exhaustive search method used for the best match, 57 SAD values are computed for the leftmost 8 8 × P block in the aforementioned 8 64 × EI area, and eight less values for each consecutive block until the last one, for which no values are computed.…”

Section: Hardware Specificationsmentioning

confidence: 99%

“…The technique utilizes the fact that the EIs can be treated as a spatial sequence of subsequent frames having a predetermined motion pattern. The most time-consuming part of the aforementioned algorithm is accelerated using a hardware platform as presented in [9], achieving real-time processing rate. Additionally, a method that is focused on the reconstruction of a fully 3D surface model is recently proposed in [10], which demonstrates several advantages compared to previous attempts on the field [11][12][13][14][15] in terms of scene size and reconstruction quality.…”

Section: Introductionmentioning

confidence: 99%

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Real-time processing pipeline for 3D imaging applications

Chaikalis

Sgouros

Maroulis

2009

2009 16th International Conference on Digital Signal Processing

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Most processing tasks in three-dimensional (3D) applications share common ground in terms of algorithm design and implementation. Furthermore, time consuming tasks like 3D reconstruction of objects from generic multiview images and compression of massive amounts of 3D image data, require enormous data processing power, and in many cases computations should be performed in real-time. In this paper we present a hardware architecture that jointly addresses both tasks. The proposed design features processing elements and memory modules that form a common compression and reconstruction datapath. Extensive pipelining minimizes throughput delays and memory access operations. Our implementation achieves real-time performance for both tasks, efficiently addressing demanding 3D imaging and video applications.

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Section: Hardware Specificationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Real-time processing pipeline for 3D imaging applications

Chaikalis

Sgouros

Maroulis

2009

2009 16th International Conference on Digital Signal Processing

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show abstract

“…Ensuring that real-time applications operate correctly depends not only on the accurate logic of the algorithms and of the results they give, but also on when results are available [5,6,7]. In recent years, computer architectures have been presented that tackle the issue of real-time from the hardware layer [8,9].…”

Section: Introductionmentioning

confidence: 99%

Adjustable compression method for still JPEG images

Mora-Pascual

Mora

Guilló

et al. 2015

Signal Processing: Image Communication

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This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting galley proof before it is published in its final citable form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain. Abstract:There are a large number of image processing applications that work with different performance requirements and available resources. Recent advances in image compression focus on reducing image size and processing time, but offer no real-time solutions for providing time/quality flexibility of the resulting image, such as using them to transmit the image contents of web pages. In this paper we propose a method for encoding still images based on the JPEG standard that allows the compression/decompression time cost and image quality to be adjusted to the needs of each application and to the bandwidth conditions of the network. The real-time control is based on a collection of adjustable parameters relating both to aspects of implementation and to the hardware with which the algorithm is processed. The proposed encoding system is evaluated in terms of compression ratio, processing delay and quality of the compressed image when compared with the standard method.

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“…The proposed implementation is based on a hardware module for the calculation of disparity vector matrices presented in [3]. With respect to our previous work, the disparity vector calculation architecture has undergone extensive pipelining in the adder tree stages, which allows achieving a higher operating frequency although more modules are added on the device.…”

Section: Introductionmentioning

confidence: 99%

Real-time compression architecture for efficient coding in autostereoscopic displays

Chaikalis

Sgouros

Maroulis

et al. 2009

J Real-Time Image Proc

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Integral imaging is a promising technique for delivering high-quality three-dimensional content. However, the large amounts of data produced during acquisition prohibits direct transmission of Integral Image data. A number of highly efficient compression architectures are proposed today that outperform standard two-dimensional encoding schemes. However, critical issues regarding realtime compression for quality demanding applications are a primary concern to currently existing Integral Image encoders. In this work we propose a real-time FPGA-based encoder for Integral Image and integral video content transmission. The proposed encoder is based on a highly efficient compression algorithm used in Integral Imaging applications. Real-time performance is achieved by realizing a pipelined architecture, taking into account the specific structure of an Integral Image. The required memory access operations are minimized by adopting a systolic concept of data flow through the core processing elements, further increasing the performance boost. The encoder targets, real-time, broadcast-type high-resolution Integral Image and video sequences and performs three orders of magnitude faster than the analogous software approach.

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Hardware implementation of a disparity estimation scheme for real-time compression in 3D imaging applications

Cited by 11 publications

References 17 publications

Real-time processing pipeline for 3D imaging applications

Real-time processing pipeline for 3D imaging applications

Adjustable compression method for still JPEG images

Real-time compression architecture for efficient coding in autostereoscopic displays

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