Hardware implementation of a pulse mode neural network-based edge detection system

Krid, Mohamed; Damak, Alima; Masmoudi, Dorra Sellami

doi:10.1016/j.aeue.2008.06.011

Cited by 15 publications

(7 citation statements)

References 13 publications

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“…For the hardware implementation, this work is drawn from a previous study of ours [6], where the gaussian function was efficiently realized by approximated it with linear functions [7]. A more detailed discussion may be found in [6].…”

Section: A Hardware Implementation Of the Input Unitmentioning

confidence: 99%

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Neural network based image denoising with pulse mode operations and hybrid on-chip learning algorithm

Gargouri

Masmoudi

2013

2013 International Conference on Control, Decision and Information Technologies (CoDIT)

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This paper proposes a pulse mode neural network (PMNN) based image denoising operation. Known by their outstanding future, PMNN is gaining support in the field of hardware implementation thanks to its significant compactness and higher density of integration. However, early pulse mode implementation suffers from some constraints due to the complexity of the on-chip learning ability, since the back-propagation algorithm is probably the most used, which costs much of hardware resources. To overcome this limitation and to provide an effective hardware implementation, we propose in this paper a hybrid learning algorithm, in which, we apply the K-means algorithm to adjust the centers positions of the basic activation functions, as well as the back-propagation algorithm to update the connection weights. The corresponding design was implemented into the FPGA platform. To evaluate the performance of the proposed approach, we consider image denoising which is a very needed step in image processing. Experimental results show good learning ability and effective generalization test.

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Section: A Hardware Implementation Of the Input Unitmentioning

confidence: 99%

“…C. Hardware implementation of the synapse unit. Fig.4 shows the block diagram of the synapse unit [7]. In which, the pulse signals provided by the hidden neurons are multiplied by the corresponding synaptic weights.…”

Section: A Hardware Implementation Of the Input Unitmentioning

confidence: 99%

Neural network based image denoising with pulse mode operations and hybrid on-chip learning algorithm

Gargouri

Masmoudi

2013

2013 International Conference on Control, Decision and Information Technologies (CoDIT)

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“…Mainly, the hardware design includes pulse encoder [8], fuzzification units, pulse multiplication units [8], conventional multipliers and adders and the parameter adjustment blocks which implement equations (7) and (10). For fuzzification module implementation, we used a previous study [9], where the Gaussian function was successfully implemented in pulse mode.…”

Section: Back-propagation Learning Algorithmmentioning

confidence: 99%

Hardware implementation of Neural-Fuzzy Network based image denoising approximation

Elloumi

Krid

Masmoudi

2014

International Image Processing, Applications and Systems Conference

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In this paper, we propose a new architecture of Neural-Fuzzy Network (NFN) devoted to function approximation tasks. NFN with on chip learning offers the possibility of reconfiguration and the generality of the solution since it can approximate any input-output function through parameters update. Back-propagation learning algorithm constitutes an appropriate method that can make an efficient approximation of NFN parameters. In this context, the main idea is to implement the proposed NFN based on the back-propagation algorithm using Field Programmable Gate Arrays (FPGA). However, the complexity of such system, presents a drawback for hardware implementation. Therefore, we make use of pulse mode since it can support this problem thanks to its higher density of integration. To verify the proposed design performance, we consider image denoising function approximation as illustration example. Experimental results reveal the performance and efficiency of the proposed NFN versus other conventional filtering techniques. Synthesis results on a FPGA platform are presented and discussed.

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“…The feasibility of multi-axes measurement has been demonstrated in several studies. However, it should be noted that most of these solutions were validated in an off-line manner, and all data were processed using a PC-based system [19]. There are few studies analyzing real-time data processing methods for newly-developed grating encoders [20][21][22].…”

Section: Introductionmentioning

confidence: 99%

An FPGA Platform for Next-Generation Grating Encoders

Han

et al. 2020

Sensors

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Among various nanometer-level displacement measurement methods, grating interferometry-based linear encoders are widely used due to their high robustness, relatively low cost, and compactness. One trend of grating encoders is multi-axis measurement capability for simultaneous precision positioning and small order error motion measurement. However, due to both lack of suitable hardware data processing platform and of a real-time displacement calculation system, meeting the requirements of real-time data processing while maintaining the nanometer order resolutions on all these axes is a challenge. To solve above-mentioned problem, in this paper we introduce a design and experimental validation of a field programmable gate array (FPGA)-cored real-time data processing platform for grating encoders. This platform includes the following functions. First, a front-end photodetector and I/V conversion analog circuit are used to realize basic analog signal filtering, while an eight-channel parallel, 16-bit precision, 200 kSPS maximum acquisition rate Analog-to-digital (ADC) is used to obtain digital signals that are easy to process. Then, an FPGA-based digital signal processing platform is implemented, which can calculate the displacement values corresponding to the phase subdivision signals in parallel and in real time at high speed. Finally, the displacement result is transferred by USB2.0 to the PC in real time through an Universal Asynchronous Receiver/Transmitter (UART) serial port to form a complete real-time displacement calculation system. The experimental results show that the system achieves real-time data processing and displacement result display while meeting the high accuracy of traditional offline data solution methods, which demonstrates the industrial potential and practicality of our absolute two-dimensional grating scale displacement measurement system.

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Hardware implementation of a pulse mode neural network-based edge detection system

Cited by 15 publications

References 13 publications

Neural network based image denoising with pulse mode operations and hybrid on-chip learning algorithm

Neural network based image denoising with pulse mode operations and hybrid on-chip learning algorithm

Hardware implementation of Neural-Fuzzy Network based image denoising approximation

An FPGA Platform for Next-Generation Grating Encoders

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