Hardware implementation of fault‐tolerance in dual computer systems

Abstract

In this paper, we propose an architectural design for a dual computer system (DCS) that operates in real-time with the fault-tolerance implemented purely by hardware. We have a novel design allowing the implementation of hardware that performs the following key services: the determination of fault type (temporary or permanent) and the localization of the faulty computer without using self-testing techniques and diagnosis routines. We also propose a non-trivial sequence of services for fault-tolerance in which the determination of the fault type and the recovery of computational processes after a temporary fault are realized before fault localization. Our design has several benefits: the designed hardware shortens the recovery point time period; the proposed non-trivial sequence of fault-tolerant services reduces (to two) the number of logical segments that should be re-run to recover the computational processes; and the determination of the fault type allows eliminating only the computer with a permanent fault. These contributions bring both an increase in system performance and an increase in the degree of system reliability.

Design and reliability analysis of the electrical control system of the subsea control module

“…Wang et al 14 proposed an optimum design of a 4-PSS-PU redundant parallel manipulator by taking the workspace, conditioning performance and acceleration into account. Samet 15,16 proposed an architectural design for a dual computer system (DCS) that operates in real-time with fault tolerance implemented purely by hardware and proposed the design of the recovery device for a dual-redundant computer system that operates in real-time.…”