Hardware Implementation of Improved Montgomery Modular Multiplication Algorithm

Abstract

This paper describes a hardware implementation of modular multiplication coprocessor for both RSA and ECC Cryptosystems. Using a self-improvement Montgomery modular multiplication algorithm, the coprocessor completes a modular multiplication with less clock cycles under the equivalent circumstance of the other designs. This modular multiplier can deal with variable operand lengths, from 128 to 2048. When adopting 64 bits multiplier, it can work at the frequency of 100MHz targeted to Virtex II XC2V250, and executes 256 bits EC point multiplication, with throughput 172k bit/s and 1024 bits RSA decryption(using CRT), with throughput 483k bit/s.

A network security system model based on FPGA

“…To implement the modular multiplication, one of the most important and complex basic operations in elliptic curve cryptography, Zhang Jiahong's improved Montgomery's modular multiplication algorithm is adopted [17]. It can deal with variable operand lengths.…”