Hardware IP Protection through Gate-Level Obfuscation

Li, Dongfang; Li, Wenchao; Zou, Xuecheng; Liu, Zhenglin

doi:10.1109/cadgraphics.2015.39

Cited by 3 publications

(2 citation statements)

References 18 publications

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“…After that, researchers all over the world attempt to focus on PUF based copyright protection techniques. Li et al [15] utilized PUF, data selector and reconfigurable logic to hide original logic functions, thereby preventing illegal attackers obtaining complete circuit netlist by reverse engineering. This technique is suitable for combinational and sequential logic circuits.…”

Section: Related Workmentioning

confidence: 99%

PUF-Based Anonymous Authentication Scheme for Hardware Devices and IPs in Edge Computing Environment

Long

Liang

et al. 2019

IEEE Access

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With rapid advances in edge computing and the Internet of Things, the security of low-layer hardware devices attract more and more attention. As an ideal hardware solution, field programmable gate array (FPGA) becomes a mainstream technology to design a complex system. The designed modules are named as intellectual property (IP) cores. In this paper, we consider both misappropriation of hardware devices and software IPs in edge computing and propose a PUF-based IP copyright anonymous authentication scheme. The scheme utilizes the double physical unclonable function (PUF) authentication model. Both the parties generate the challenge jointly in authentication to avoid replay attack and modeling attack on PUF circuit. The complexity of authentication is greatly reduced. Besides, the server of FPGA vendor is unnecessary to store all the challenge response pairs (CRPs) of each PUF-based chip due to the use of the double PUF authentication model. It saves the system resource and achieves better security. To protect software IP, IP core vendor inserts copyright information and anonymous buyer identity information into the design before trading. The anonymity of the buyer ensures the benefits of the buyer. With the participation of trustable device vendor, infringement behavior can be traced according to extracted fingerprints. The experiments show that the resource overhead of the proposed scheme is reduced by 61.96% and 31.61% by comparing with 2-1 DAPUF and built-in self-adjustable PUF. Besides, PUF stability is 99.54%. It demonstrates the good performance of the proposed scheme. INDEX TERMS Edge computing, field programmable gate array (FPGA), IP cores, PUF authentication model, anonymous authentication.

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Section: Related Workmentioning

confidence: 99%

PUF-Based Anonymous Authentication Scheme for Hardware Devices and IPs in Edge Computing Environment

Long

Liang

et al. 2019

IEEE Access

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“…research and development costs) is required in integrated chip design, and therefore, intellectual property (IP) reuse reduces development costs. 1 However, there is potential for abuse, such as illegal resale and forgery of the reused IP, which has financial implications for the IP designer and affects the IP designer's competitive advantage. The Virtual Socket Interface Alliance (VSIA) was established to protect the IP of integrated circuit designers, and IP protection for integrated circuits is a topic of ongoing interest.…”

Section: Introductionmentioning

confidence: 99%

Intellectual property protection for FPGA designs using the public key cryptography

Huang

et al. 2019

Advances in Mechanical Engineering

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For the copyright protection in intellectual property reuse technology, we must ensure that when an intellectual property watermark verifier leaks the secret key of an intellectual property watermark system, a malicious attacker could not guess the key to facilitate successful attacks on the watermarks. Therefore, this work proposes a robust intellectual property watermarking algorithm based on elliptic-curve cryptography. The physical layout of intellectual property design is abstracted into a graph with tree structure by using the topology theory. A secure model based on the asymmetric encryption model is proposed to encrypt the watermark positions. The generated graph and a random searching algorithm are used for the distribution of the watermark positions. Finally, the watermarks are inserted by reordering the redundant attributes in the graph. The experiments show that the proposed algorithm will insert more watermark constraints under the same condition. Thus, the probability of coincidence is lower, achieving good reliability. In addition, when the watermarks are impaired due to attacks, the algorithm can restore the original watermarks from the topology graph. In comparison to other algorithms, the proposed algorithm has good performance in watermark capacity and overhead, as well as provides resilience to the typical attacks.

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Physical Unclonable Functions based Hardware Obfuscation Techniques: A State of the Art

Kareem

Dunaev

2021

2021 16th Iberian Conference on Information Systems and Technologies (CISTI)

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Hardware IP Protection through Gate-Level Obfuscation

Cited by 3 publications

References 18 publications

PUF-Based Anonymous Authentication Scheme for Hardware Devices and IPs in Edge Computing Environment

PUF-Based Anonymous Authentication Scheme for Hardware Devices and IPs in Edge Computing Environment

Intellectual property protection for FPGA designs using the public key cryptography

Physical Unclonable Functions based Hardware Obfuscation Techniques: A State of the Art

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