2022
DOI: 10.1007/978-3-031-21867-5_10
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Hardware Isolation Support for Low-Cost SoC-FPGAs

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Cited by 3 publications
(2 citation statements)
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“…The OS and Application layers are implemented on the Application Processing Unit, which has a dual-core Cortex-A9. Since the selected MPSoC-FPGA has no isolation mechanism, we have used Protection Units (PUs) IP cores, as proposed in our previous work [46]. These PUs provide isolation support between PS-PL and PL-PL communication for MPSoC-FPGAs of the AMD-Xilinx series 7 family.…”
Section: B Centralize Control Unitmentioning
confidence: 99%
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“…The OS and Application layers are implemented on the Application Processing Unit, which has a dual-core Cortex-A9. Since the selected MPSoC-FPGA has no isolation mechanism, we have used Protection Units (PUs) IP cores, as proposed in our previous work [46]. These PUs provide isolation support between PS-PL and PL-PL communication for MPSoC-FPGAs of the AMD-Xilinx series 7 family.…”
Section: B Centralize Control Unitmentioning
confidence: 99%
“…For safety issues, the various units responsible for different components are isolated through the Protection Unit proposed by authors in Ref. [46]. In fact, with the proposed solution, the slave-client nodes, such as the DMS, X-ray tube, and the HV module, must only implement the FSMs required for controlling the internal modules and setting them for the safe mode.…”
Section: Distributed Control Unitmentioning
confidence: 99%