Hardware Obfuscation of AES IP Core Using PUFs and PRNG: A Secure Cryptographic Key Generation Solution for Internet-of-Things Applications

Chhabra, Surbhi; Lata, Kusum

doi:10.1007/s42979-022-01194-x

Cited by 3 publications

(4 citation statements)

References 49 publications

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“…Kumar et al [72] provide a detailed explanation of a public/private key pair-based strategy for safeguarding the use of intellectual property cores in FPGAs. [129], (b) key sharing [130], (c) authentication [131], (d) software protection [132], (e) random number generation [16], (f) key generation [133], (g) ID generation [104] and (h) logic obfuscation [134].…”

Section: Ip Protectionmentioning

confidence: 99%

“…This per-device PUF setup step uses 2689 flip-flops and 2199 LUTs on the Xilinx Virtex-7 FPGA to limit the amount of space needed for PUFs and error correction during key generation. Chhabra et al [133] have integrated with the key-based hardware obfuscation of AES IP core by generating the cryptographic key using PUFs. Their experimental results also show that the proposed model is resilient against side-channel and SAT-based attacks.…”

Section: Secret Key Generationmentioning

confidence: 99%

“…By using PUF-generated values as part of the logic, it becomes challenging for attackers to reverse-engineer or understand the design. Chhabra et al [133] have integrated with the key-based hardware logic obfuscation of AES IP core by generating the cryptographic key using PUFs. Their experimental results also show that the proposed model is resilient against side-channel and SAT-based attacks.…”

Section: Logic Obfuscationmentioning

confidence: 99%

“…Figure 20. Applications of FPGA-based PUFs in various domains (a) IP protection[129], (b) key sharing[130], (c) authentication[131], (d) software protection[132], (e) random number generation[16], (f) key generation[133], (g) ID generation[104] and (h) logic obfuscation[134].…”

mentioning

confidence: 99%

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FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis

Lata,

Cenkeramaddi

2023

Cryptography

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Field-programmable gate arrays (FPGAs) have firmly established themselves as dynamic platforms for the implementation of physical unclonable functions (PUFs). Their intrinsic reconfigurability and profound implications for enhancing hardware security make them an invaluable asset in this realm. This groundbreaking study not only dives deep into the universe of FPGA-based PUF designs but also offers a comprehensive overview coupled with a discerning comparative analysis. PUFs are the bedrock of device authentication and key generation and the fortification of secure cryptographic protocols. Unleashing the potential of FPGA technology expands the horizons of PUF integration across diverse hardware systems. We set out to understand the fundamental ideas behind PUF and how crucially important it is to current security paradigms. Different FPGA-based PUF solutions, including static, dynamic, and hybrid systems, are closely examined. Each design paradigm is painstakingly examined to reveal its special qualities, functional nuances, and weaknesses. We closely assess a variety of performance metrics, including those related to distinctiveness, reliability, and resilience against hostile threats. We compare various FPGA-based PUF systems against one another to expose their unique advantages and disadvantages. This study provides system designers and security professionals with the crucial information they need to choose the best PUF design for their particular applications. Our paper provides a comprehensive view of the functionality, security capabilities, and prospective applications of FPGA-based PUF systems. The depth of knowledge gained from this research advances the field of hardware security, enabling security practitioners, researchers, and designers to make wise decisions when deciding on and implementing FPGA-based PUF solutions.

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