Hardware Partitioning Using Parallel Genetic Algorithm to Improve the Performance of Multi-core CPU

Nayak, Suryakanta; Panda, Mrutyunjaya

doi:10.1007/978-981-15-2774-6_55

Cited by 3 publications

(2 citation statements)

References 12 publications

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“…When it comes to multi-core processors having shared caches, two main ways to improve scheduling efficiency are cache partitioning and explicitly measuring the quantity of cache interference across activities. The first method has poor schedulability performance because of very negative cache interference estimates, whereas the second method may cause jobs to take longer to execute because of less cache utilisation, which is bad for schedulability as well [1] . As the lag time among processing power with main memory access delay has increased, cache memory has become an integral part of CPU design.…”

Section: Introductionmentioning

confidence: 99%

Examining partitioned caches performance in heterogeneous multi-core processors

Yenugula

2022

Int. J. Commun. Inf. Technol.

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The last-level cache (LLC) is shared by many distinct kinds of cores in asymmetric multi-core systems. There is greater rivalry in the LLC since different core types have different memory access needs. Our new technique for replacing the split cache, HAPC, takes heterogeneity into account. To improve coreto-core interference, this method uses cache partitioning. In multithreaded applications, it guides the replacement strategy by monitoring the shared reuse state of every cache block inside the partition during runtime. This ensures that cache blocks shared among different cores are maintained. For huge cores to make more efficient LLC visits, cache replacement algorithms generally modify the leftover state while preserving cache blocks needed by them. This approach takes into consideration the fact that heterogeneous cores have different memory accesses to LLC. In comparison to the state-of-the-art cache substitute's algorithms, LRU and SRCP, HAPC can greatly enhance the performance of large cores when running multithreaded applications, with almost no impact on small cores, leading to an overall improvement in system performance.

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Section: Introductionmentioning

confidence: 99%

Examining partitioned caches performance in heterogeneous multi-core processors

Yenugula

2022

Int. J. Commun. Inf. Technol.

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“…These, in turn, expressively increase the time complexity of the organized algorithm. Therefore, many researchers try to examine parallelization methods for GA on multi-core systems as well as many-core systems [15]. A common approach is to migrate the computation of fitness, *Corresponding Author Institutional Email: abbasi@basu.ac.ir (M. Abbasi) mutation, crossover, and selection functions to parallel machines [16].…”

Section: Introductionmentioning

confidence: 99%

Efficient Parallelization of a Genetic Algorithm Solution on the Traveling Salesman Problem with Multi-core and Many-core Systems

Abbasi

Rafiee

2020

IJE

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Efficient parallelization of genetic algorithms (GAs) on state-of-the-art multi-threading or manythreading platforms is a challenge due to the difficulty of scheduling hardware resources regarding the concurrency of threads. In this paper, for resolving the problem, a novel method is proposed, which parallelizes the GA by designing three concurrent kernels, each of which are running some dependent effective operators of GA. The proposed method can be straightforwardly adapted to run on many-core and multi-core processors by using Compute Unified Device Architecture (CUDA) and Threading Building Blocks (TBB) platforms. To efficiently use the valuable resources of such computing cores in concurrent execution of the GA, threads that run any of the triple kernels are synchronized by a considerably fast switching technique. The offered method was used for parallelizing a GA-based solution of Traveling Salesman Problem (TSP) over CUDA and TBB platforms with identical settings. The results confirm the superiority of the proposed method to state-of-the-art methods in effective parallelization of GAs on Graphics Processing Units (GPUs) as well as on multi-core Central Processing Units (CPUs). Also, for GA problems with a modest initial population, though the switching time among GPU kernels is negligible, the TBB-based parallel GA exploits the resources more efficiently.

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An efficient lightweight algorithm for scheduling tasks onto dynamically reconfigurable hardware using graph-oriented simulated annealing

Mollajafari

2023

Neural Comput & Applic

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Hardware Partitioning Using Parallel Genetic Algorithm to Improve the Performance of Multi-core CPU

Cited by 3 publications

References 12 publications

Examining partitioned caches performance in heterogeneous multi-core processors

Examining partitioned caches performance in heterogeneous multi-core processors

Efficient Parallelization of a Genetic Algorithm Solution on the Traveling Salesman Problem with Multi-core and Many-core Systems

An efficient lightweight algorithm for scheduling tasks onto dynamically reconfigurable hardware using graph-oriented simulated annealing

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