Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon

Heo, Jeong Wook; Jeong, Kwangok; Choi, Jong Seob; Kim, Taewhan; Choi, Kyu-Myung

doi:10.1109/tcad.2021.3095824

Cited by 2 publications

(2 citation statements)

References 41 publications

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“…As the feature node size of integrated circuits decreases, the process, voltage, temperature (PVT), and aging variations significantly impact digital circuit timing [1]. Worst-case guard band designs, including voltage or frequency guard bands [2,3], used to prevent circuit timing errors are not enough, because these designs can adversely affect circuit performance or increase power consumption, offsetting the advantage of process scaling. For large-scale circuits and shrinking CMOS technology, timing reliability is more challenging [4].…”

Section: Introductionmentioning

confidence: 99%

BPath-RO: A Performance- and Area-Efficient In Situ Delay Measurement Scheme for Digital IC

Li,

Liang,

Zhang

et al. 2023

Electronics

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Circuit delays are increasingly sensitive to process, voltage, temperature, and aging (PVTA) variations, severely impacting circuit performance. Accurate measurement of circuit delay is essential. However, the additional hardware structures for measuring circuit delay add to the critical path delay. To address this issue, this paper proposes a bypass-based ring oscillator (BPath-RO) that reduces the impact on the critical path delay by moving the added measurement control structures to the bypass. The proposed measurement scheme requires only two transistors inserted into the critical path, which is more conducive to engineering change order (ECO). Measurement simulation experiments were performed on representative critical paths of the ISCAS’89 s298 and ITC’99 b15 benchmark circuits. The experimental results show that, in comparison with the existing architectures, the Bpath-RO delay measurement scheme improves the circuit performance by an average of 13.81% (s298) and 3.47% (b15) and reduces the hardware overhead by up to 70% for each path.

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Section: Introductionmentioning

confidence: 99%

BPath-RO: A Performance- and Area-Efficient In Situ Delay Measurement Scheme for Digital IC

Li,

Liang,

Zhang

et al. 2023

Electronics

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“…With the development of the microelectronics craft technique, modern IC design attaches great importance to the Performance, Power, and Area (PPA) of chips [1][2][3]. The technique of reducing the supply voltage to near-threshold voltage (NTV) region is receiving more attention in recent years due to remarkable energy efficiency improvement but suffers from severe challenges of performance variation for Static Timing Analysis (STA) [4][5][6]. In order to guarantee timing closure, an extra timing margin has to be added to compensate for pessimistic timing estimation at the cost of unneglectable area and power overhead [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Timing Analysis and Optimization Method with Interdependent Flip-Flop Timing Model for Near-Threshold Design

2022

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Near-threshold Voltage (NTV) design is receiving wide attention due to remarkable energy efficiency improvement at the cost of performance degradation. The interdependency between the setup–hold time and clock-to-q delay of flip-flops has been exploited in the Super-threshold Voltage (STV) domain to improve circuit performance but faces the severe challenge of nonlinear relationship and wider effective coverage in the NTV region, which prevents the application of interdependent flip-flop model for timing analysis and optimization for NTV design. In this paper, a novel interdependent flip-flop timing model is proposed by Artificial Neural Network (ANN) to predict the clock-to-q delay with training data generated by SPICE simulation in a restricted hexagonal area of the two-dimensional setup-hold time space. By integrating the proposed model into Static Timing Analysis (STA) flow, a novel iterative optimization method is proposed to improve performance for NVT circuits based on a Genetic Algorithm (GA). The proposed timing analysis and optimization method were validated under Semiconductor Manufacturing International Corporation (SMIC) 40 nm process at the voltage of 0.6 V with the International Symposium on Circuits and Systems (ISCAS)’89 benchmark circuits. Experimental results demonstrate that the ANN-based interdependent timing model for flip-flop achieves considerable accurate prediction with the Mean Absolute Relative Error (MARE) of less than 0.69%. The minimum clock periods for ISCAS’89 benchmark circuits are reduced by 1.70~6.28% compared to traditional STA results without any setup and hold violations and hardware cost, which achieves at most 6.7% performance improvement for NTV design.

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Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon

Cited by 2 publications

References 41 publications

BPath-RO: A Performance- and Area-Efficient In Situ Delay Measurement Scheme for Digital IC

BPath-RO: A Performance- and Area-Efficient In Situ Delay Measurement Scheme for Digital IC

Timing Analysis and Optimization Method with Interdependent Flip-Flop Timing Model for Near-Threshold Design

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