Hardware read-write lock elision

Felber, Pascal; Issa, Shady; Matveev, Alexander; Romano, Paolo

doi:10.1145/2901318.2901346

Cited by 11 publications

(5 citation statements)

References 18 publications

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“…Therefore, in application scenarios with a high read/write ratio, its performance is not as good as that of race-free reader-writer locks. It is only suitable for application scenarios with obvious NUMA characteristics and a low reader-writer ratio [20] .…”

Section: Algorithm and Implementationmentioning

confidence: 99%

Design and implementation of a scalable self-adaptive reader-writer lock for multi-core systems

Cai¹,

Qiu²,

Yao³

et al. 2023

International Conference on Computer Graphics, Artificial Intelligence, and Data Processing (ICCAID 2022)

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With the rapid development of multi-core processor technology, parallelization has become the main approach for modern applications to improve throughput and responsiveness. However, the increasing number of processors also poses a challenge to the scalability of parallel program performance. In a traditional single-threaded program, all data is exclusively occupied by one thread, so the performance optimization of the program mainly focuses on the algorithm logic and implementation skills of the program; while in the multi-core system environment, most multi-threaded applications have performance scalability bottleneck. That is, the application cannot make full use of the performance advantages of multiple cores, and its performance decreases as the number of processors increases. The key factor restricting the improvement of performance scalability is often the synchronization mechanism of multi-core systems. Reader-writer lock is a synchronization mechanism that divides the operation to access shared resources or data into reader lock and writer lock, which enables effective cooperation between multiple different threads and ensures that applications can operate in a multicore environment with logical consistency. However, from another perspective, the reader-writer lock mechanism also limits the scalability of concurrent execution of applications. In application scenarios with different reader/writer ratios, the performance of reader-writer locks also differs, restricting the scalability of the performance of applications in multicore systems. Therefore, in a multi-core environment, it is of practical significance to implement a new type of readerwriter lock with scalable performance. This new reader-writer lock may automatically adjust the lock acquisition path according to the read/write ratio of the application scenario. In view of the shortcomings of the current reader-writer locks, this paper proposes a simple, efficient, optimized, and easy-to-implement adaptive reader-writer lock mechanism and interface which is suitable for multi-core environments, as well as application scenarios with different read/, write ratios. This mechanism gives full play to the high performance of multi-core systems and automatically adjusts lock acquisition according to different application scenarios. There are only minor changes to the application by replacing the original reader-writer lock instance and API interface function calls with an adaptive reader-writer lock instance and the API interface function calls for the adaptive reader-writer lock. The mechanism enables good scalability and improves the concurrency and scalability of reader-writer locks in multi-core systems in application scenarios with different read/write ratios. It will be conducive to meeting the growing demand for low latency, high throughput, and high concurrency processors.

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Section: Algorithm and Implementationmentioning

confidence: 99%

Design and implementation of a scalable self-adaptive reader-writer lock for multi-core systems

Cai¹,

Qiu²,

Yao³

et al. 2023

International Conference on Computer Graphics, Artificial Intelligence, and Data Processing (ICCAID 2022)

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“…• In many realistic workloads, transactions read a much larger number of memory positions than they write to [16]. As such, the read-sets of T CP U and T GP U are likely to be much larger than their corresponding write-sets.…”

Section: Basic Algorithmmentioning

confidence: 99%

HeTM: Transactional Memory for Heterogeneous Systems

Castro

Romano

Ilić

et al. 2019

2019 28th International Conference on Parallel Architectures and Compilation Techniques (PACT)

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Modern heterogeneous computing architectures, which couple multi-core CPUs with discrete many-core GPUs (or other specialized hardware accelerators), enable unprecedented peak performance and energy efficiency levels. Unfortunately, though, developing applications that can take full advantage of the potential of heterogeneous systems is a notoriously hard task. This work takes a step towards reducing the complexity of programming heterogeneous systems by introducing the abstraction of Heterogeneous Transactional Memory (HeTM). HeTM provides programmers with the illusion of a single memory region, shared among the CPUs and the (discrete) GPU(s) of a heterogeneous system, with support for atomic transactions. Besides introducing the abstract semantics and programming model of HeTM, we present the design and evaluation of a concrete implementation of the proposed abstraction, which we named Speculative HeTM (SHeTM). SHeTM makes use of a novel design that leverages on speculative techniques and aims at hiding the inherently large communication latency between CPUs and discrete GPUs and at minimizing inter-device synchronization overhead. SHeTM is based on a modular and extensible design that allows for easily integrating alternative TM implementations on the CPU's and GPU's sides, which allows the flexibility to adopt, on either side, the TM implementation (e.g., in hardware or software) that best fits the applications' workload and the architectural characteristics of the processing unit. We demonstrate the efficiency of the SHeTM via an extensive quantitative study based both on synthetic benchmarks and on a porting of a popular object caching system.

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“…Finally, P8TM builds on and extends on HERWL [16], where we introduced the idea of using POWER8's suspend-resume and ROT facilities to elide read-write locks. Besides targeting a different application domain (transactional programs vs. lock elision), P8TM integrates a set of novel techniques.…”

Section: I S C 2 0 1 7 28:4 Extending Hardware Transactional Memory Capacitymentioning

confidence: 99%

Extending hardware transactional memory capacity via rollback-only transactions and suspend/resume

et al. 2019

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Transactional memory (TM) aims at simplifying concurrent programming via the familiar abstraction of atomic transactions. Recently, Intel and IBM have integrated hardware based TM (HTM) implementations in commodity processors, paving the way for the mainstream adoption of the TM paradigm. Yet, existing HTM implementations suffer from a crucial limitation, which hampers the adoption of HTM as a general technique for regulating concurrent access to shared memory: the inability to execute transactions whose working sets exceed the capacity of CPU caches. In this paper we propose P8TM, a novel approach that mitigates this limitation on IBM's POWER8 architecture by leveraging a key combination of techniques: uninstrumented read-only transactions, Rollback Only Transaction-based update transactions, HTM-friendly (software-based) read-set tracking, and self-tuning. P8TM can dynamically switch between different execution modes to best adapt to the nature of the transactions and the experienced abort patterns. Indepth evaluation with several benchmarks indicates that P8TM can achieve striking performance gains in workloads that stress the capacity limitations of HTM, while achieving performance on par with HTM even in unfavourable workloads.

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Hardware read-write lock elision

Cited by 11 publications

References 18 publications

Design and implementation of a scalable self-adaptive reader-writer lock for multi-core systems

Design and implementation of a scalable self-adaptive reader-writer lock for multi-core systems

HeTM: Transactional Memory for Heterogeneous Systems

Extending hardware transactional memory capacity via rollback-only transactions and suspend/resume

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