Hardware resource estimation for heterogeneous FPGA-based SoCs

Makni, Mariem; Baklouti, Mouna; Niar, Smaïl; Abid, Mohamed

doi:10.1145/3019612.3019683

Cited by 8 publications

(3 citation statements)

References 10 publications

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“…Process control, task scheduling, and interface for data processing modules are defined as a software development toolkit (SDK) API-based software application. Baklouti, Mouna, et al [17] have previously highlighted the advantages of an FPGA-based SoC architecture. Figure 2 illustrates the high-level architecture, consisting of the control unit, data processing unit, and memory management unit.…”

Section: System Architecture and Design Methodologymentioning

confidence: 99%

Scalable QKD Postprocessing System With Reconfigurable Hardware Accelerator

Venkatachalam,

Shingala,

et al. 2023

IEEE Trans. Quantum Eng.

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Key Distillation is an essential component of every quantum key distribution (QKD) system because it compensates for the inherent transmission errors of a quantum channel. However, the interoperability and throughput aspects of the post-processing components are often neglected. In this paper, we propose a high-throughput key distillation framework that supports multiple QKD protocols, implemented in a field-programmable gate array (FPGA). The proposed design adapts a MapReduce programming model to efficiently process large chunks of raw data across the limited computing resources of an FPGA. We present a novel hardware-efficient integrated post-processing architecture that offers dynamic error correction, mutual authentication with a physically unclonable function, and an inbuilt high-speed encryption application that utilizes the key for secure communication. Additionally, we have developed a semi-automated high-level synthesis (HLS) framework that is compatible with any discrete variable QKD system, showing promising speedup. Overall, the experimental results demonstrate a noteworthy enhancement in scalability achieved through the utilization of a single FPGA platform.

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Section: System Architecture and Design Methodologymentioning

confidence: 99%

Scalable QKD Postprocessing System With Reconfigurable Hardware Accelerator

Venkatachalam,

Shingala,

et al. 2023

IEEE Trans. Quantum Eng.

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“…In Reference [49] a similar technique is used to estimate the resource usage for HLS tools. The input is C/C++ code with a selected number of HLS pragmas.…”

Section: Related Workmentioning

confidence: 99%

On Predictable Reconfigurable System Design

Voss

Kwaadgras

Mencer

et al. 2021

ACM Trans. Archit. Code Optim.

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We propose a design methodology to facilitate rigorous development of complex applications targeting reconfigurable hardware. Our methodology relies on analytical estimation of system performance and area utilisation for a given specific application and a particular system instance consisting of a controlflow machine working in conjunction with one or more reconfigurable dataflow accelerators. The targeted application is carefully analyzed, and the parts identified for hardware acceleration are reimplemented as a set of representative software models. Next, with the results of the application analysis, a suitable system architecture is devised and its performance is evaluated to determine bottlenecks, allowing predictable design. The architecture is iteratively refined, until the final version satisfying the specification requirements in terms of performance and required hardware area is obtained. We validate the presented methodology using a widely accepted convolutional neural network (VGG-16) and an important HPC application (BQCD). In both cases, our methodology relieved and alleviated all system bottlenecks before the hardware implementation was started. As a result the architectures were implemented first time right, achieving state-of-the-art performance within 15% of our modelling estimations.

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“…A high-level but accurate analytic hardware resource estimator for FPGA HLS accelerators is presented in [163]. The estimator uses models for FPGA hardware resources (such as DSPs, BRAMs, LUTs and Flip-flops) to explore the trade-off between HLS optimisation directives and the area occupied on the target FPGA with no need to generate the HDL.…”

Section: ) Loop Pipeliningmentioning

confidence: 99%

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

et al. 2020

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Heterogeneous computing systems with tightly coupled processors and reconfigurable logic blocks provide great scope to improve software performance by executing each section of code on the processor or custom hardware accelerator that best matches its requirements and the system optimisation goals. This paper is motivated by the idea of a software tool that can automatically accomplish the task of deploying code, originally written for a conventional computer, to the processors and reconfigurable logic blocks in a heterogeneous system. We undertake an extensive survey of high-level synthesis tools to determine how close we are to this vision, and to identify any capability gaps. The survey is structured according to a new framework that clearly expresses the relationships between the many tools surveyed. We find that none of the existing tools can deploy general high-level code without manual intervention. Logic synthesis from arbitrary high-level code remains an open problem with dynamic data structures, function pointers and recursion all presenting challenges. Other challenges include automating the tasks of code partitioning, optimisation and design space exploration.

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Hardware resource estimation for heterogeneous FPGA-based SoCs

Cited by 8 publications

References 10 publications

Scalable QKD Postprocessing System With Reconfigurable Hardware Accelerator

Scalable QKD Postprocessing System With Reconfigurable Hardware Accelerator

On Predictable Reconfigurable System Design

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

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